c738c96519
Erase virtual registers that are unused after DCE.
...
llvm-svn: 127773
2011-03-16 22:56:13 +00:00
e29d63e98a
Tag cached interference with a user-provided tag instead of the virtual register number.
...
The live range of a virtual register may change which invalidates the cached
interference information.
llvm-svn: 127772
2011-03-16 22:56:11 +00:00
557a82c099
Clarify debugging output.
...
llvm-svn: 127771
2011-03-16 22:56:08 +00:00
ac106273d4
The x86-64 ABI says that a bool is only guaranteed to be sign-extended to a byte
...
rather than an int. Thankfully, this only causes LLVM to miss optimizations, not
generate incorrect code.
This just fixes the zext at the return. We still insert an i32 ZextAssert when
reading a function's arguments, but it is followed by a truncate and another i8
ZextAssert so it is not optimized.
llvm-svn: 127766
2011-03-16 22:20:18 +00:00
40a9200357
Rename a test to be more inclusive.
...
llvm-svn: 127765
2011-03-16 22:20:12 +00:00
d1ad9bc277
Don't recompute something that we already have in a local variable.
...
llvm-svn: 127764
2011-03-16 22:20:07 +00:00
fd95b016fb
Revert r127757, "Patch to a fix dwarf relocation problem on ARM. One-line fix
...
plus the test where it used to break.", which broke Clang self-host of a
Debug+Asserts compiler, on OS X.
llvm-svn: 127763
2011-03-16 22:16:39 +00:00
c871eff3f5
Add XCore intrinsics for setclk, setrdy.
...
llvm-svn: 127761
2011-03-16 21:56:00 +00:00
a3aeafeb35
Patch to a fix dwarf relocation problem on ARM. One-line fix plus the test where it used to break.
...
llvm-svn: 127757
2011-03-16 21:05:52 +00:00
49e354bcb6
Add a test for i1 zeroext arguments on x86-64. We currently generate code that
...
conforms to the ABI, but DAGCombine could in theory recognize the sequence of
zext asserts and truncates and generate incorrect code.
llvm-svn: 127754
2011-03-16 20:15:44 +00:00
d4346f2388
Add checkevent intrinsic to check if any resources owned by the current thread
...
can event.
llvm-svn: 127741
2011-03-16 18:34:00 +00:00
d60e4101e6
test/CodeGen/X86: FileCheck-ize and add actions for x86_64-linux and x86_64-win32.
...
llvm-svn: 127734
2011-03-16 13:53:07 +00:00
0b9e2b0257
test/CodeGen/X86: Add a pattern for Win64.
...
llvm-svn: 127733
2011-03-16 13:52:51 +00:00
c10801e8a5
test/CodeGen/X86: FileCheck-ize and add explicit -mtriple=x86_64-linux. They are useless to Win64 target.
...
llvm-svn: 127732
2011-03-16 13:52:38 +00:00
662892df27
test/CodeGen/X86/byval*.ll: Win64 has not supported byval yet.
...
llvm-svn: 127731
2011-03-16 13:52:20 +00:00
406f02c9ea
test/CodeGen/X86/dyn-stackalloc.ll: FileCheck-ize.
...
llvm-svn: 127730
2011-03-16 13:52:08 +00:00
7599b106b7
Fix a comment.
...
llvm-svn: 127728
2011-03-16 08:13:42 +00:00
76e68ea916
lib/Support/raw_ostream.cpp: On mingw, report_fatal_error() should not be called at dtor context.
...
report_fatal_error() invokes exit(). We know report_fatal_error() might not write messages to stderr when any errors were detected on FD == 2.
llvm-svn: 127726
2011-03-16 02:53:39 +00:00
a3d4749e24
Windows/PathV2.inc: [PR8520] Recognize "NUL" as special (character) file.
...
FIXME: It is a temporal hack. We should detect as many "special file name" as possible.
llvm-svn: 127724
2011-03-16 02:53:32 +00:00
aaa9b4f824
Windows/Path.inc: [PR6270] PathV1::makeUnique(): Give arbitrary initial seed for workaround.
...
FIXME: We should use sys::fs::unique_file() in future.
llvm-svn: 127723
2011-03-16 02:53:24 +00:00
c91fa6d19f
Tidy up. Whitespace and 80 column.
...
llvm-svn: 127721
2011-03-16 01:21:55 +00:00
39c041cae7
Do not accidently initialize NumDbgValueLost and NumDbgLineLost counts.
...
llvm-svn: 127720
2011-03-16 00:27:57 +00:00
0454253d7a
Only convert allocas to scalars if it is profitable. The profitability metric I
...
chose is having a non-memcpy/memset use and being larger than any native integer
type. Originally I chose having an access of a size smaller than the total size
of the alloca, but this caused some minor issues on the spirit benchmark where
SRoA runs again after some inlining.
This fixes <rdar://problem/8613163>.
llvm-svn: 127718
2011-03-16 00:13:44 +00:00
7b0f3c6a1a
Add native integer type TargetData to some existing tests.
...
llvm-svn: 127717
2011-03-16 00:13:40 +00:00
b51c830f7c
Better use initializer lists.
...
llvm-svn: 127716
2011-03-16 00:13:37 +00:00
63062ccf85
Add a clarifying comment.
...
llvm-svn: 127715
2011-03-16 00:13:35 +00:00
51e76763c7
Add TargetData::fitsInLegalInteger().
...
llvm-svn: 127714
2011-03-16 00:13:28 +00:00
a4c3154fca
There were two issues fixed:
...
1. The ARM Darwin *r9 call instructions were pseudo-ized recently.
Modify the ARMDisassemblerCore.cpp file to accomodate the change.
2. The disassembler was unnecessarily adding 8 to the sign-extended imm24:
imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate)
// Encoding A1
It has no business doing such. Removed the offending logic.
Add test cases to arm-tests.txt.
llvm-svn: 127707
2011-03-15 22:27:33 +00:00
d0332e4efe
Add scei vendor
...
llvm-svn: 127705
2011-03-15 21:51:56 +00:00
865f8b592a
The VTBL (and VTBX) instructions are rather permissive concerning the masks they
...
accept. If a value in the mask is out of range, it uses the value 0, for VTBL,
or leaves the value unchanged, for VTBX.
llvm-svn: 127700
2011-03-15 21:15:20 +00:00
a0d5ec10d1
Trace back through sibling copies to hoist spills and find rematerializable defs.
...
After live range splitting, an original value may be available in multiple
registers. Tracing back through the registers containing the same value, find
the best place to insert a spill, determine if the value has already been
spilled, or discover a reaching def that may be rematerialized.
This is only the analysis part. The information is not used for anything yet.
llvm-svn: 127698
2011-03-15 21:13:25 +00:00
32210de3e4
Preserve both isPHIDef and isDefByCopy bits when copying parent values.
...
llvm-svn: 127697
2011-03-15 21:13:22 +00:00
920139ca08
lit/ProgressBar.py: [PR7919] Improve line wrap for XN-incapable terminals.
...
On Win32 console, emitting char to col#79 causes linefeed, and the cursor will not return to col#79 upper line with backspace.
llvm-svn: 127696
2011-03-15 21:07:44 +00:00
ebecb33307
Some minor cleanups based on feedback.
...
llvm-svn: 127694
2011-03-15 20:47:26 +00:00
4ae30b6785
Trailing whitespae.
...
llvm-svn: 127691
2011-03-15 20:25:54 +00:00
dbb27393cc
Clean up something noticed by Fritz.
...
llvm-svn: 127684
2011-03-15 18:42:33 +00:00
42401d6af2
Do not form thumb2 ldrd / strd if the offset is by multiple of 4. rdar://9133587
...
llvm-svn: 127683
2011-03-15 18:41:52 +00:00
024932fc77
Don't indent cases in a switch, no functionality change.
...
llvm-svn: 127681
2011-03-15 15:55:30 +00:00
5f1a26ea39
On the XCore the scavenging slot should be closest to the SP.
...
llvm-svn: 127680
2011-03-15 15:10:11 +00:00
638b8b783f
is_llvm_target_library: recognize libraries without the LLVM prefix.
...
Without this cmake fails at configuration when some target pass
"native" on LLVM_LINK_COMPONENTS and that is expanded to "X86".
llvm-svn: 127679
2011-03-15 14:53:53 +00:00
3a68eb150b
Add XCore intrinsics for getps, setps, setsr and clrsr.
...
llvm-svn: 127678
2011-03-15 13:45:47 +00:00
94751fbf32
PTX: Set PTX 2.0 as the minimum supported version
...
- Remove PTX 1.4 code generation
- Change type of intrinsics to .v4.i32 instead of .v4.i16
- Add and/or/xor integer instructions
llvm-svn: 127677
2011-03-15 13:24:15 +00:00
c2631d26c0
Silence compiler warning about case values not being in the enumerated type
...
MCFixupKind. This is the same technique that is used elsewhere in MC.
llvm-svn: 127676
2011-03-15 08:54:51 +00:00
7921ac0975
Avoid a compiler warning about reg possibly being used uninitialized
...
when building with assertions disabled.
llvm-svn: 127675
2011-03-15 08:41:24 +00:00
0b8cdfb6ec
Do not add PHIs with no users when creating LCSSA form. Patch by Andrew Clinton.
...
llvm-svn: 127674
2011-03-15 07:41:25 +00:00
c1f8658368
Add C++ global operator {new,new[],delete,delete[]}(unsigned {int,long}) to the
...
memory builtins as equivalent to malloc/free.
This is different from any attribute we have. For example, you can delete the
allocators when their result is unused, but you can't collapse two calls to the
same function, even if no global/memory state has changed in between. The
noalias return states that the result does not alias any other pointer, but
instcombine optimizes malloc() as though the result is non-null for the purpose
of eliminating unused pointers.
llvm-svn: 127673
2011-03-15 07:31:32 +00:00
e4b8ac9fef
Add a peephole optimization to optimize pairs of bitcasts. e.g.
...
v2 = bitcast v1
...
v3 = bitcast v2
...
= v3
=>
v2 = bitcast v1
...
= v1
if v1 and v3 are of in the same register class.
bitcast between i32 and fp (and others) are often not nops since they
are in different register classes. These bitcast instructions are often
left because they are in different basic blocks and cannot be
eliminated by dag combine.
rdar://9104514
llvm-svn: 127668
2011-03-15 05:13:13 +00:00
880e299dcd
- Add "Bitcast" target instruction property for instructions which perform
...
nothing more than a bitcast.
- Teach tablegen to automatically infer "Bitcast" property.
llvm-svn: 127667
2011-03-15 05:09:26 +00:00
c4414c6e92
PR9450: Make switch optimization in SimplifyCFG not dependent on the ordering
...
of pointers in an std::map.
llvm-svn: 127650
2011-03-15 02:23:35 +00:00
c5c2cfa381
sext(undef) = 0, because the top bits will all be the same.
...
zext(undef) = 0, because the top bits will be zero.
llvm-svn: 127649
2011-03-15 02:22:10 +00:00
928de16793
Testcase for r127630.
...
llvm-svn: 127648
2011-03-15 01:49:08 +00:00
f2f4837de3
Basic sanity checks to ensure that 2- and 3-byte
...
VEX prefixes are working for triadic AVX
instructions. This concludes the patch set to
enable AVX support for the X86 disassebler.
llvm-svn: 127647
2011-03-15 01:32:46 +00:00
b60b0bc47e
Enabled disassembler support for AVX instructions
...
in the instruction tables and fixed a few bugs that
were causing decode conflicts. Rudimentary tests
are coming up in the next patch.
llvm-svn: 127646
2011-03-15 01:28:15 +00:00
c3fd523731
X86 table-generator and disassembler support for the AVX
...
instruction set. This code adds support for the VEX prefix
and for the YMM registers accessible on AVX-enabled
architectures. Instruction table support that enables AVX
instructions for the disassembler is in an upcoming patch.
llvm-svn: 127644
2011-03-15 01:23:15 +00:00
a34f1b1f10
Remove getMinusSCEVForExitTest().
...
This function performed acrobatics to prove no-self-wrap, which we now
have for free.
llvm-svn: 127643
2011-03-15 01:16:14 +00:00
7a2873dfbe
Fixed an ARM disassembler bug where it does not handle STRi12 correctly because an extra
...
register operand was erroneously added. Remove an incorrect assert which triggers the bug.
rdar://problem/9131529
llvm-svn: 127642
2011-03-15 01:13:17 +00:00
5c25a92011
There are some situations which can cause the URoR hack to infinitely recurse
...
and then go kablooie. The problem was that it was tracking the PHI nodes anew
each time into this function. But it didn't need to. And because the recursion
didn't know that a PHINode was visited before, it would go ahead and call
itself.
There is a testcase, but unfortunately it's too big to add. This problem will go
away with the EH rewrite.
<rdar://problem/8856298>
llvm-svn: 127640
2011-03-15 01:03:17 +00:00
f6b01ff422
Propagate SCEV no-wrap flags whenever possible.
...
This needs review.
llvm-svn: 127638
2011-03-15 00:37:00 +00:00
3af6fe66b9
Clean up ARM tail calls a bit. They're pseudo-instructions for normal branches.
...
Also more cleanly separate the ARM vs. Thumb functionality. Previously, the
encoding would be incorrect for some Thumb instructions (the indirect calls).
llvm-svn: 127637
2011-03-15 00:30:40 +00:00
2139d3148f
If we don't know how long a string is we can't fold an _chk version to the
...
normal version.
Fixes rdar://9123638
llvm-svn: 127636
2011-03-15 00:25:41 +00:00
dfeda09345
Make llvm::Consumer a class (to remove a MSVC warning since Consumer is later forward declared as a struct)
...
llvm-svn: 127632
2011-03-14 23:07:21 +00:00
e1fd78f2bc
Generate a VTBL instruction instead of a series of loads and stores when we
...
can. As Nate pointed out, VTBL isn't super performant, but it *has* to be better
than this:
_shuf:
@ BB#0: @ %entry
push {r4, r7, lr}
add r7, sp, #4
sub sp, #12
mov r4, sp
bic r4, r4, #7
mov sp, r4
mov r2, sp
vmov d16, r0, r1
orr r0, r2, #6
orr r3, r2, #7
vst1.8 {d16[0]}, [r3]
vst1.8 {d16[5]}, [r0]
subs r4, r7, #4
orr r0, r2, #5
vst1.8 {d16[4]}, [r0]
orr r0, r2, #4
vst1.8 {d16[4]}, [r0]
orr r0, r2, #3
vst1.8 {d16[0]}, [r0]
orr r0, r2, #2
vst1.8 {d16[2]}, [r0]
orr r0, r2, #1
vst1.8 {d16[1]}, [r0]
vst1.8 {d16[3]}, [r2]
vldr.64 d16, [sp]
vmov r0, r1, d16
mov sp, r4
pop {r4, r7, pc}
The "illegal" testcase in vext.ll is no longer illegal.
<rdar://problem/9078775>
llvm-svn: 127630
2011-03-14 23:02:38 +00:00
e2eb807601
Version N of the llvm_unreachable patch: VC++ doesn't recognize that abort()
...
doesn't return, so just go back to using the old runtime function instead
of trying to use abort() when __builtin_unreachable (or an equivalent) isn't
supported.
llvm-svn: 127629
2011-03-14 22:41:50 +00:00
4b6ae939ca
This patch is a big refactoring of llvm-diff. It doesn't add new features, but it re-organizes the old features, so I can insert the MetadataEngine to use the same infrastructure.
...
llvm-svn: 127627
2011-03-14 22:22:46 +00:00
c9a16d581d
Check that the AsmParser exists for the native target to enable initialization
...
function.
llvm-svn: 127626
2011-03-14 22:12:35 +00:00
d3cc9fdd8e
Fix this test up a bit.
...
llvm-svn: 127621
2011-03-14 21:05:21 +00:00
d97a665cff
Trailing whitespace.
...
llvm-svn: 127620
2011-03-14 20:59:06 +00:00
0fabf10388
Ignore isCodeGenOnly instructions when generating diassembly tables.
...
llvm-svn: 127619
2011-03-14 20:58:49 +00:00
59a549b7ec
Place context in member variables instead of passing around pointers.
...
Use the opportunity to get rid of the trailing underscore variable names.
llvm-svn: 127618
2011-03-14 20:57:14 +00:00
c525e3a114
Okay, some compilers complain if you provide the exception-specification
...
where none was before. Just don't declare it and hope it's declared
in every translation unit that needs it.
llvm-svn: 127612
2011-03-14 20:20:29 +00:00
b9b8ea4018
Fix the exception-specification of abort() when declaring it in C++.
...
llvm-svn: 127610
2011-03-14 20:10:50 +00:00
0491c0124f
Make llvm_unreachable evaluate to __builtin_unreachable() in -Asserts
...
builds, which was the apparent consensus of PR8973 and llvmdev.
llvm-svn: 127608
2011-03-14 20:01:21 +00:00
a00bab24c2
Rename members to match LLVM naming conventions more closely.
...
Remove the unused reserved_ bit vector, no functional change intended.
This doesn't break 'svn blame', this file really is all my fault.
llvm-svn: 127607
2011-03-14 19:56:43 +00:00
c5efcbad71
Remove some dead patterns.
...
llvm-svn: 127601
2011-03-14 18:34:35 +00:00
37139edc8c
BIT_CONVERT has been renamed to BITCAST.
...
llvm-svn: 127600
2011-03-14 18:19:52 +00:00
d2f3b01797
Minor optimization. sign-ext/anyext of undef is still undef.
...
llvm-svn: 127598
2011-03-14 18:15:55 +00:00
383ecd873b
Indentation.
...
llvm-svn: 127595
2011-03-14 18:02:30 +00:00
e92dcceab7
Negating a recurrence preserves no-self-wrap.
...
llvm-svn: 127593
2011-03-14 17:38:54 +00:00
876ee079fc
Trailing whitespace.
...
llvm-svn: 127592
2011-03-14 17:32:49 +00:00
f1781db622
HowFarToZero can compute a trip count as long as the recurrence has no-self-wrap.
...
llvm-svn: 127591
2011-03-14 17:28:02 +00:00
8b55b736b1
Added SCEV::NoWrapFlags to manage unsigned, signed, and self wrap
...
properties.
Added the self-wrap flag for SCEV::AddRecExpr.
A slew of temporary FIXMEs indicate the intention of the no-self-wrap flag
without changing behavior in this revision.
llvm-svn: 127590
2011-03-14 16:50:06 +00:00
328b223bb1
whitespace
...
llvm-svn: 127589
2011-03-14 16:48:10 +00:00
fbc8d301bf
PTX: Emit global arrays with proper sizes
...
- Emit all arrays as type .b8 and proper sizes in bytes to conform
to the output of nvcc
llvm-svn: 127584
2011-03-14 15:40:11 +00:00
8509380f83
PTX: Add support for sqrt/sin/cos intrinsics
...
llvm-svn: 127578
2011-03-14 14:09:33 +00:00
a19f075974
ptx: add set.p instruction and related changes to predicate execution
...
llvm-svn: 127577
2011-03-14 11:26:01 +00:00
6e2d823235
Emacs mode string.
...
llvm-svn: 127576
2011-03-14 04:20:57 +00:00
0fc06eefad
Correct small comment order typo.
...
llvm-svn: 127575
2011-03-14 02:30:32 +00:00
b452db02f0
This case is solved by Scalar Replacement of Aggregates (DT) and
...
Early CSE pass so this patch reverts it to original source code.
llvm-svn: 127574
2011-03-14 01:21:00 +00:00
58bae0e957
ptx: add basic support of predicate execution
...
llvm-svn: 127569
2011-03-13 17:26:00 +00:00
b7538c71e1
Add comment as following:
...
load and store reference same memory location, the memory location
is represented by getelementptr with two uses (load and store) and
the getelementptr's base is alloca with single use. At this point,
instructions from alloca to store can be removed.
(this pattern is generated when bitfield is accessed.)
For example,
%u = alloca %struct.test, align 4 ; [#uses=1]
%0 = getelementptr inbounds %struct.test* %u, i32 0, i32 0;[#uses=2]
%1 = load i8* %0, align 4 ; [#uses=1]
%2 = and i8 %1, -16 ; [#uses=1]
%3 = or i8 %2, 5 ; [#uses=1]
store i8 %3, i8* %0, align 4
llvm-svn: 127565
2011-03-13 14:05:51 +00:00
ac824ee462
LTO is not ready for Windows.
...
llvm-svn: 127562
2011-03-13 03:06:59 +00:00
e1539cc5b6
Now that we are deleting unused live intervals during allocation, pointers may be reused.
...
Use the virtual register number as a cache tag instead. They are not reused.
llvm-svn: 127561
2011-03-13 01:29:32 +00:00
43a87501b3
Tell the register allocator about new unused virtual registers.
...
This allows the allocator to free any resources used by the virtual register,
including physical register assignments.
llvm-svn: 127560
2011-03-13 01:23:11 +00:00
3685f2762b
Build EnhancedDisassembly as a shared library too.
...
llvm-svn: 127555
2011-03-12 22:01:47 +00:00
dc352c4c04
Build CompilerDriver library.
...
llvm-svn: 127554
2011-03-12 22:01:42 +00:00
02c446a73a
Build LTO as a static library too.
...
llvm-svn: 127553
2011-03-12 22:01:36 +00:00
68c1f55fdc
Build LTO as a static library too.
...
llvm-svn: 127549
2011-03-12 17:32:30 +00:00
5acc751b6f
Teach ComputeMaskedBits about sub nsw.
...
llvm-svn: 127548
2011-03-12 17:18:11 +00:00
cc48b9ac0f
Whe we build a shared library, add its list of used libraries to the
...
link command.
Fixed a pair of IF expressions too.
llvm-svn: 127546
2011-03-12 16:48:54 +00:00
1fc0c8ab78
Update link components for llvm-dis and LTO.
...
llvm-svn: 127545
2011-03-12 16:48:49 +00:00
b847bf547b
Speculatively revert commit 127478 (jsjodin) in an attempt to fix the
...
llvm-gcc-i386-linux-selfhost and llvm-x86_64-linux-checks buildbots.
The original log entry:
Remove optimization emitting a reference insted of label difference, since
it can create more relocations. Removed isBaseAddressKnownZero method,
because it is no longer used.
llvm-svn: 127540
2011-03-12 13:07:37 +00:00
2e939f7c3c
This patch removes some of useless instructions generated by bitfield access.
...
llvm-svn: 127539
2011-03-12 12:18:44 +00:00
e77005ef88
Include snippets in the live stack interval.
...
llvm-svn: 127530
2011-03-12 04:25:36 +00:00
a86595e06b
Spill multiple registers at once.
...
Live range splitting can create a number of small live ranges containing only a
single real use. Spill these small live ranges along with the large range they
are connected to with copies. This enables memory operand folding and maximizes
the spill to fill distance.
Work in progress with known bugs.
llvm-svn: 127529
2011-03-12 04:17:20 +00:00
47f660aeaf
Fixed the comparison operator for the enhanced
...
disassembler's disassembler map.
llvm-svn: 127527
2011-03-12 03:27:54 +00:00
dae1dc1f01
That's it, I am declaring this a failure of the C++03 STL.
...
There are too many compatibility problems with using mixed types in
std::upper_bound, and I don't want to spend 110 lines of boilerplate setting up
a call to a 10-line function. Binary search is not /that/ hard to implement
correctly.
I tried terminating the binary search with a linear search, but that actually
made the algorithm slower against my expectation. Most live intervals have less
than 4 segments. The early test against endIndex() does pay, and this version is
25% faster than plain std::upper_bound().
llvm-svn: 127522
2011-03-12 01:50:35 +00:00
c313d94068
Saving files before committing is overrated.
...
Add a RUN line to this test.
llvm-svn: 127520
2011-03-12 01:36:23 +00:00
174d872702
Sometimes isPredicable lies to us and tells us we don't need the operands.
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Go ahead and add them on when we might want to use them and let
later passes remove them.
Fixes rdar://9118569
llvm-svn: 127518
2011-03-12 01:09:29 +00:00
fcc34cacd9
Remove no-longer-correct special case for disasm of ARM BL instructions.
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llvm-svn: 127517
2011-03-12 01:05:29 +00:00
965fe994c2
Add FIXME.
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llvm-svn: 127516
2011-03-12 00:51:00 +00:00
3f2096eafe
Pseudo-ize the ARM Darwin *r9 call instruction definitions. They're the same
...
actual instruction as the non-Darwin defs, but have different call-clobber
semantics and so need separate patterns. They don't need to duplicate the
encoding information, however.
llvm-svn: 127515
2011-03-12 00:45:26 +00:00
b7c6e8f575
Add a FIXME.
...
llvm-svn: 127511
2011-03-11 23:25:21 +00:00
f026d9ed53
Pseudo-ize the ARM 'B' instruction.
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llvm-svn: 127510
2011-03-11 23:24:15 +00:00
2fee5327aa
Remove dead code. These ARM instruction definitions no longer exist.
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llvm-svn: 127509
2011-03-11 23:15:02 +00:00
376d5e8772
Remove dead code. These ARM instruction definitions no longer exist.
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llvm-svn: 127508
2011-03-11 23:11:41 +00:00
bb0547d9c4
Pseudo-ize VMOVDcc and VMOVScc.
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llvm-svn: 127506
2011-03-11 23:09:50 +00:00
9f2b3b569b
80 columns
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llvm-svn: 127505
2011-03-11 23:00:16 +00:00
6d371ce37e
Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side-
...
effect that we get proper instruction printing using the "pop" mnemonic for it.
llvm-svn: 127502
2011-03-11 22:51:41 +00:00
338d362200
Roll r127459 back in:
...
Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.
This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.
llvm-svn: 127498
2011-03-11 21:52:04 +00:00
4d7d728594
Fix the GCC test suite issue exposed by r127477, which was caused by stack
...
protector insertion not working correctly with unreachable code. Since that
revision was rolled out, this test doesn't actual fail before this fix.
llvm-svn: 127497
2011-03-11 21:51:56 +00:00
66443c034d
Teach FastISel to support register-immediate-immediate instructions.
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llvm-svn: 127496
2011-03-11 21:33:55 +00:00
ec62d28ae1
80 columns.
...
llvm-svn: 127495
2011-03-11 21:02:27 +00:00
d767d06b26
Trailing whitespace.
...
llvm-svn: 127493
2011-03-11 20:59:19 +00:00
52594d99e4
Remove dead code. These ARM instruction definitions don't exist.
...
llvm-svn: 127491
2011-03-11 20:51:07 +00:00
59eea670f8
ARM VDUPfd and VDUPfq can just be patterns. The instruction is the same
...
as for VDUP32d and VDUP32q, respectively.
llvm-svn: 127489
2011-03-11 20:44:08 +00:00
6c609d626f
Remove dead code. These ARM instruction definitions don't exist.
...
llvm-svn: 127488
2011-03-11 20:38:18 +00:00
c77dea7f55
ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q
...
and VDUPLN32d, respectively.
llvm-svn: 127486
2011-03-11 20:31:17 +00:00
24fe5e36ea
ARM VREV64df and VREV64qf can just be patterns. The instruction is the same
...
as for VREV64d32 and VREV64q32, respectively.
llvm-svn: 127485
2011-03-11 20:18:05 +00:00
0b5119315b
This FIXME has been fixed.
...
llvm-svn: 127483
2011-03-11 20:07:37 +00:00
fa56bca781
Properly pseudo-ize ARM MVNCCi.
...
llvm-svn: 127482
2011-03-11 19:55:55 +00:00
730e1c2c9e
Add missing 'return on failure'. Previously we'd crash after emitting
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the diagnostic.
llvm-svn: 127480
2011-03-11 19:52:52 +00:00
f3f78583f9
Remove optimization emitting a reference insted of label difference, since it can create more relocations. Removed isBaseAddressKnownZero method, because it is no longer used.
...
llvm-svn: 127478
2011-03-11 19:37:02 +00:00
94ccb27b43
Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often get
...
created from the", it broke some GCC test suite tests.
llvm-svn: 127477
2011-03-11 19:30:30 +00:00
0122841626
Force re-linking of LLVMgold.so when its exports file changes.
...
llvm-svn: 127473
2011-03-11 18:27:13 +00:00
87e4a4da0d
Fix processing of gold.exports.
...
llvm-svn: 127471
2011-03-11 18:07:46 +00:00
982efb5c89
While printing annotations, print line number and variable name if debug info is present.
...
llvm-svn: 127470
2011-03-11 18:07:33 +00:00
f541bfd7d4
Fix MOVCCi32imm to be have ARM-mode Requires and a proper size (8 bytes, was 4).
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llvm-svn: 127469
2011-03-11 18:00:42 +00:00
710d5da306
Replace -dag-chain-limit flag with constant. It has survived a release cycle without being touched, so no longer needs to pollute the hidden-help text.
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llvm-svn: 127468
2011-03-11 17:46:59 +00:00
64d05bc281
Add LTO and gold plugin to the CMake build. Linux-only, support for
...
other systems pending.
PR9456.
llvm-svn: 127466
2011-03-11 15:44:24 +00:00
391a946fa9
ComputeMaskedBits: sub falls through to add, and sub doesn't have the same overflow semantics as add.
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Should fix the selfhost failures that started with r127463.
llvm-svn: 127465
2011-03-11 14:46:49 +00:00
51897bcd3e
InstCombine: Fix a thinko where transform an icmp under the assumption that it's a zero comparison when it's not.
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Fixes PR9454.
llvm-svn: 127464
2011-03-11 11:37:40 +00:00
cc79973856
Teach ComputeMaskedBits about nsw on add. I don't think there's anything we can
...
do with nuw here, but sub and mul should be given similar treatment.
Fixes PR9343 #15 !
llvm-svn: 127463
2011-03-11 09:00:19 +00:00
8559f5914c
Fix use of CompEnd predicate to be standards conforming
...
The existing CompEnd predicate does not define a strict weak order as required
by the C++03 standard; therefore, its use as a predicate to std::upper_bound
is invalid. For a discussion of this issue, see
http://www.open-std.org/jtc1/sc22/wg21/docs/lwg-defects.html#270
This patch replaces the asymmetrical comparison with an iterator adaptor that
achieves the same effect while being strictly standard-conforming by ensuring
an apples-to-apples comparison.
llvm-svn: 127462
2011-03-11 08:54:34 +00:00
cc27b3acc4
Optimize trivial branches in CodeGenPrepare, which often get created from the
...
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.
This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.
llvm-svn: 127459
2011-03-11 04:54:27 +00:00
f17b0031f3
Teach TableGen to pre-calculate register enum values when creating the
...
CodeGenRegister entries. Use this information to more intelligently build
the literal register entires in the DAGISel matcher table. Specifically,
use a single-byte OPC_EmitRegister entry for registers with a value of
less than 256 and OPC_EmitRegister2 entry for registers with a larger value.
rdar://9066491
llvm-svn: 127456
2011-03-11 02:19:02 +00:00
05a23b1e61
silence a conditional assignment -Wuninitialized warning.
...
llvm-svn: 127453
2011-03-11 02:12:51 +00:00
eb52c23646
Make the register enum value part of the CodeGenRegister struct.
...
llvm-svn: 127448
2011-03-11 01:33:54 +00:00
f910bf29a9
Trailing whitespace.
...
llvm-svn: 127447
2011-03-11 01:27:24 +00:00
b1ac770fa3
Trailing whitespace.
...
llvm-svn: 127446
2011-03-11 01:19:05 +00:00
d0fc231e13
Tidy up since ARM MOVCCi and MOVCCi16 are now pseudos.
...
llvm-svn: 127445
2011-03-11 01:16:49 +00:00
Jakob Stoklund Olesen