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54 Commits

Author SHA1 Message Date
Johnny Chen 48592ee5af Thumb2 BFC was insufficiently encoded. 
rdar://problem/9292717

llvm-svn: 129619
 2011-04-15 22:52:15 +00:00
Johnny Chen 4251b151b1 Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations. 
llvm-svn: 129531
 2011-04-14 19:13:28 +00:00
Johnny Chen d0fb04f437 Thumb disassembler did not handle tBRIND (indirect branch) properly. 
rdar://problem/9280370

llvm-svn: 129480
 2011-04-13 21:59:01 +00:00
Johnny Chen ffa6378fd6 The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt. 
rdar://problem/9279440

llvm-svn: 129469
 2011-04-13 21:04:32 +00:00
Johnny Chen 70591cbc60 Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as such. 
rdar://problem/9276651

llvm-svn: 129462
 2011-04-13 19:46:05 +00:00
Johnny Chen 0d306a7840 Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was not properly handled. 
rdar://problem/9276427

llvm-svn: 129456
 2011-04-13 17:51:02 +00:00
Johnny Chen 3c2f74c9f3 Add sanity check for Ld/St Dual forms of Thumb2 instructions. 
rdar://problem/9273947

llvm-svn: 129411
 2011-04-12 23:31:00 +00:00
Johnny Chen 960eef3db3 The Thumb2 RFE instructions need to have their second halfword fully specified. 
In addition, the base register is not rGPR, but GPR with th exception that:

    if n == 15 then UNPREDICTABLE

rdar://problem/9273836

llvm-svn: 129391
 2011-04-12 21:41:51 +00:00
Johnny Chen 01637b9acb Add bad register checks for Thumb2 Ld/St instructions. 
rdar://problem/9269047

llvm-svn: 129387
 2011-04-12 21:17:51 +00:00
Johnny Chen ab86a519f8 The Thumb2 Ld, St, and Preload instructions with the i12 forms should have its Inst{23} 
be specified as '1' (add = TRUE).

Also add a utility function for Thumb2.

llvm-svn: 129377
 2011-04-12 18:48:00 +00:00
Johnny Chen d0e2be39ea Print out a debug message when the reglist fails the sanity check for Thumb Ld/St Multiple. 
llvm-svn: 129365
 2011-04-12 17:09:04 +00:00
Johnny Chen 672ef14a62 A8.6.16 B 
Encoding T1 (tBcc)
if cond == '1110' then UNDEFINED;

rdar://problem/9268681

llvm-svn: 129325
 2011-04-12 00:14:49 +00:00
Johnny Chen dc8bf9ec08 Thumb disassembler was erroneously rejecting "blx sp" instruction. 
rdar://problem/9267838

llvm-svn: 129320
 2011-04-11 23:33:30 +00:00
Johnny Chen f79d5365de Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled. 
rdar://problem/9266265

llvm-svn: 129298
 2011-04-11 21:14:35 +00:00
Kevin Enderby 9377a52c12 Adding support for printing operands symbolically to llvm's public 'C' 
disassembler API.  Hooked this up to the ARM target so such tools as Darwin's
otool(1) can now print things like branch targets for example this:
  blx _puts
instead of this:
  blx #-36
And even print the expression encoded in the Mach-O relocation entried for
things like this:
  movt r0, :upper16:((_foo-_bar)+1234)

llvm-svn: 129284
 2011-04-11 18:08:50 +00:00
Johnny Chen 875e0e4626 Sanity check the option operand for DMB/DSB. 
PR9648
rdar://problem/9257634

llvm-svn: 129146
 2011-04-08 19:18:07 +00:00
Johnny Chen f9cd139369 Fix ARM disassembly for PLD/PLDW/PLI which suffers from code rot and add some test cases. 
Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly.

llvm-svn: 128417
 2011-03-28 18:41:58 +00:00
Johnny Chen 923f3dac01 Fixed the t2PLD and friends disassembly and add two test cases. 
llvm-svn: 128322
 2011-03-26 01:32:48 +00:00
Johnny Chen 49316e40ba Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode GPRRegClassID. 
Also add some test cases.

rdar://problem/9189829

llvm-svn: 128304
 2011-03-25 22:19:07 +00:00
Johnny Chen aaf2c69400 DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass. Add two test cases. 
rdar://problem/9182892

llvm-svn: 128299
 2011-03-25 19:35:37 +00:00
Johnny Chen b35548f44d Modify DisassembleThumb2LdStEx() to be more robust/correct in light of recent change to 
t2LDREX/t2STREX instructions.  Add two test cases.

llvm-svn: 128293
 2011-03-25 18:29:49 +00:00
Johnny Chen a52143bff3 Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the register classes were changed), 
modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1.

llvm-svn: 128252
 2011-03-25 01:09:48 +00:00
Johnny Chen 6469ca0c33 T2 Load/Store Multiple: 
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt.  Also add a test case.

llvm-svn: 128240
 2011-03-24 21:36:56 +00:00
Matt Beaumont-Gay bfd23e4009 Avoid -Wunused-variable in -asserts builds 
llvm-svn: 128048
 2011-03-22 00:37:28 +00:00
Johnny Chen e387f8a5e9 The disassembler for Thumb was wrongly adding 4 to the computed imm32 offset. 
Remove the offending logic and update the test cases.

llvm-svn: 127843
 2011-03-18 00:38:03 +00:00
Johnny Chen 221a014ea3 It used to be that t_addrmode_s4 was used for both: 
o A8.6.195 STR (register) -- Encoding T1
o A8.6.193 STR (immediate, Thumb) -- Encoding T1

It has been changed so that now they use different addressing modes
and thus different MC representation (Operand Infos).  Modify the
disassembler to reflect the change, and add relevant tests.

llvm-svn: 127833
 2011-03-17 22:04:05 +00:00
Kevin Enderby 63b0d108a2 Add missing whitespace in the formatting. 
llvm-svn: 126687
 2011-02-28 21:45:12 +00:00
Kevin Enderby 58775fea6f Fix the arm's disassembler for blx that was building an MCInst without the 
needed two predicate operands before the imm operand.

llvm-svn: 126662
 2011-02-28 18:46:31 +00:00
Bruno Cardoso Lopes 9cd43977c3 Add assembly parsing support for "msr" and also fix its encoding. Also add 
testcases for the disassembler to make sure it still works for "msr".

llvm-svn: 125948
 2011-02-18 19:45:59 +00:00
Bruno Cardoso Lopes 90d1dfe4c6 Fix encoding and add parsing support for the arm/thumb CPS instruction: 
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
  from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
  wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.

llvm-svn: 125489
 2011-02-14 13:09:44 +00:00
Owen Anderson 4ebf471c9b Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. 
llvm-svn: 125127
 2011-02-08 22:39:40 +00:00
Owen Anderson 99ea8a3510 Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it. 
llvm-svn: 121082
 2010-12-07 00:45:21 +00:00
Owen Anderson 8335e8fa63 Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. This allows the 
Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free.
It also allows us to fold away at least one codegen-only pattern.

llvm-svn: 120481
 2010-11-30 22:45:47 +00:00
Jim Grosbach 7ec3d34553 Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw 
instructions. This simplifies instruction printing and disassembly.

llvm-svn: 120333
 2010-11-29 22:37:40 +00:00
Bill Wendling a68e3a5397 Encode the multi-load/store instructions with their respective modes ('ia', 
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>

llvm-svn: 119310
 2010-11-16 01:16:36 +00:00
Evan Cheng 6f36042557 Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536. 
llvm-svn: 118152
 2010-11-03 05:14:24 +00:00
Jim Grosbach d100ed858e Detabify and clean up 80 column violations. 
llvm-svn: 116454
 2010-10-13 23:47:11 +00:00
Bob Wilson 942b10f511 Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid 
printing "lsl #0".  This fixes the remaining parts of pr7792.  Make
corresponding changes for encoding/decoding these instructions.

llvm-svn: 111251
 2010-08-17 17:23:19 +00:00
Bob Wilson 15b3c3d0ac Move the Thumb2 SSAT and USAT optional shift operator out of the 
instruction opcode.  This fixes part of PR7792.

llvm-svn: 111047
 2010-08-13 21:48:10 +00:00
Bob Wilson d3a828ce68 Refactor the code for disassembling Thumb2 saturate instructions along the 
same lines as the change I made for ARM saturate instructions.

llvm-svn: 111029
 2010-08-13 19:04:21 +00:00
Johnny Chen d59c73f998 Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm. 
Added two test cases to arm-tests.txt.

llvm-svn: 110880
 2010-08-11 23:35:12 +00:00
Jim Grosbach d343166a0b Many Thumb2 instructions can reference the full ARM register set (i.e., 
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
  mls r0,r9,r0,sp
instead of:
  mov r2, sp
  mls r0, r9, r0, r2

This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.

PR7499

llvm-svn: 109842
 2010-07-30 02:41:01 +00:00
Jim Grosbach 11013eda5a Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction 
and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.

llvm-svn: 108570
 2010-07-16 23:05:05 +00:00
Dan Gohman 882bb2984e Start TargetRegisterClass indices at 0 instead of 1, so that 
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.

llvm-svn: 106296
 2010-06-18 18:13:55 +00:00
Johnny Chen d85afee134 Modified some assert() msg strings; no other functionality change. 
llvm-svn: 102008
 2010-04-21 18:37:48 +00:00
Johnny Chen dd56c40591 Thumb instructions which have reglist operands at the end and predicate operands 
before reglist were not properly handled with respect to IT Block.  Fix that by
creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those
instructions for disassembly.  Add a test case.

llvm-svn: 101974
 2010-04-21 01:01:19 +00:00
Johnny Chen 8bcc00b43e Better error-handling of getBitFieldInvMask() where msb < lsb (encoding error), 
instead of just asserting.

llvm-svn: 101942
 2010-04-20 21:29:28 +00:00
Johnny Chen 2161e9f03b Better error-handling for DisassembleThumb2DPModImm() with 2-reg operands where 
d==15 is considered illegal.  Return false instead of assert().

llvm-svn: 101852
 2010-04-20 01:01:57 +00:00
Johnny Chen 25df2a75bd Better error-handling for DisassembleThumb2DPSoReg() where the 3-reg operand 
instructions should have Rd (Inst{11-8}) != 0b1111.

Ref: A6.3 32-bit Thumb instruction encoding
     A6.3.11 Data-processing (shifted register)
llvm-svn: 101788
 2010-04-19 17:16:40 +00:00
Johnny Chen 0175ec1263 Wrap the error msgs in DEBUG() macro so that they won't appear in NDEBUG build. 
llvm-svn: 101329
 2010-04-15 01:20:56 +00:00