Commit Graph

291327 Commits

Author SHA1 Message Date
Alex Bradbury 6cfb31c7c1 [AVR] Fix build after r334078
r334078 added MCSubtargetInfo to fixupNeedsRelaxation and applyFixup. This 
patch makes the necessary adjustment for the AVR target.

llvm-svn: 334202
2018-06-07 15:29:09 +00:00
Simon Pilgrim 51ff15f472 [X86][SSE] Simplify combineVectorTruncationWithPACKUS. NFCI.
Move code only used by combineVectorTruncationWithPACKUS out of combineVectorTruncation.

llvm-svn: 334201
2018-06-07 14:53:32 +00:00
Roman Lebedev 847938925b [NFC][InstSimplify] Add tests for shl nuw C, %x -> C fold.
%r = shl nuw i8 C, %x

As per langref: If the nuw keyword is present, then the shift produces
                a poison value if it shifts out any non-zero bits.
Thus, if the sign bit is set on C, then %x can only be 0,
which means that %r can only be C.

https://rise4fun.com/Alive/WMk
Was mentioned in D47428 review.

llvm-svn: 334200
2018-06-07 14:18:38 +00:00
Sanjay Patel 898fbd7c47 [x86] add tests for backwards propagate mask bug (PR37060, PR37667); NFC
llvm-svn: 334199
2018-06-07 14:11:18 +00:00
Pavel Labath d44638eb2b DIERef: move trivial constructors into the header
This enables more inlining/optimization opportunities for a fairly
critical class.

NFCI

llvm-svn: 334198
2018-06-07 14:03:30 +00:00
Guillaume Chatelet b4f1582ac5 [llvm-exegesis] Make BenchmarkRunner handle multiple configurations.
Summary: BenchmarkRunner subclasses can now create many configurations - although this patch still generates one.

Reviewers: courbet

Subscribers: tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D47877

llvm-svn: 334197
2018-06-07 14:00:29 +00:00
Paul Semel cb0f043cec [llvm-objdump] Add -R option
This option prints dynamic relocation entries of the given file

Differential Revision: https://reviews.llvm.org/D47493

llvm-svn: 334196
2018-06-07 13:30:55 +00:00
Hiroshi Inoue 01ef4c2c64 [PowerPC] avoid unprofitable Repl32 flag in BitPermutationSelector
BitPermutationSelector sets Repl32 flag for bit groups which can be (potentially) benefit from 32-bit rotate-and-mask instructions with bit replication, i.e. rlwinm/rlwimi copies lower 32 bits into upper 32 bits on 64-bit PowerPC before rotation.
However, enforcing 32-bit instruction sometimes results in redundant generated code.
For example, the following simple code is compiled into rotldi + rlwimi while it can be compiled into only rldimi instruction if Repl32 flag is not set on the bit group for (a & 0xFFFFFFFF).

uint64_t func(uint64_t a, uint64_t b) {
	return (a & 0xFFFFFFFF) | (b << 32) ;
}

To avoid such problem, this patch checks the potential benefit of Repl32 flag before setting it. If a bit group does not require rotation (i.e. RLAmt == 0) and won't be merged into another group, we do not benefit from Repl32 flag on this group.

Differential Revision: https://reviews.llvm.org/D47867

llvm-svn: 334195
2018-06-07 13:21:14 +00:00
Petar Jovanovic 241f286bd7 [Mips] Silencing warnings in instruction info (NFC)
isORCopyInst and isReadOrWriteToDSPReg functions were producing warning
that some statements my fall through.

Patch by Nikola Prica.

Differential Revision: https://reviews.llvm.org/D47876

llvm-svn: 334194
2018-06-07 13:06:06 +00:00
Simon Pilgrim 09953d8412 [X86][SSE] Simplify combineVectorTruncationWithPACKSS to reduce code duplication
Simplify combineVectorTruncationWithPACKSS to just a SIGN_EXTEND_INREG followed by using the existing truncateVectorWithPACK instead of duplicating code.

llvm-svn: 334193
2018-06-07 13:01:42 +00:00
Sam McCall 4caa85129f [clangd] Code completion: drop explicit injected names/operators, ignore Sema priority
Summary:
Now we have most of Sema's code completion signals incorporated in Quality,
which will allow us to give consistent ranking to sema/index results.

Therefore we can/should stop using Sema priority as an explicit signal.
This fixes some issues like namespaces always having a terrible score.

The most important missing signals are:
 - Really dumb/rarely useful completions like:
    SomeStruct().^SomeStruct
    SomeStruct().^operator=
    SomeStruct().~SomeStruct()
   We already filter out destructors, this patch adds injected names and
   operators to that list.
 - type matching the expression context.
   Ilya has a plan to add this in a way that's compatible with indexes
   (design doc should be shared real soon now!)

Reviewers: ioeric

Subscribers: ilya-biryukov, MaskRay, jkorous, cfe-commits

Differential Revision: https://reviews.llvm.org/D47871

llvm-svn: 334192
2018-06-07 12:49:17 +00:00
Hiroshi Inoue b557846083 [PowerPC] fix trivial typos in comment, NFC
llvm-svn: 334191
2018-06-07 12:49:12 +00:00
Pavel Labath 6938969223 DebugNamesDWARFIndex: Add type lookup suport
This implements just one of the GetTypes overloads. The other is not
testable from lldb-test so I'm leaving it unimplemented until I figure
out what to do with testing.

llvm-svn: 334190
2018-06-07 12:26:18 +00:00
Matt Arsenault f1c868ef08 AMDGPU: Fix not including v2f64 in SReg_128
Fixes assertion with calls returning v2f64.

llvm-svn: 334189
2018-06-07 12:16:31 +00:00
Simon Pilgrim 0e29d8d81f [X86][SSE] Add extra trunc(shl) test cases
The existing trunc_shl_17_v8i16_v8i32 test case should (but doesn't) fold to zero, I've added 2 new test cases:
 - trunc_shl_16_v8i16_v8i32 which folds to zero (this is actually testing the target faux shuffle combine)
 - trunc_shl_15_v8i16_v8i32 which should perform the full shl + truncate

llvm-svn: 334188
2018-06-07 11:22:52 +00:00
Florian Hahn 0d6b01761c [Mem2Reg] Avoid replacing load with itself in promoteSingleBlockAlloca.
We do the same thing in rewriteSingleStoreAlloca.

Fixes PR37632.

Reviewers: chandlerc, davide, efriedma

Reviewed By: davide

Differential Revision: https://reviews.llvm.org/D47825

llvm-svn: 334187
2018-06-07 11:09:05 +00:00
Pavel Labath 6675e652a3 DebugNamesDWARFIndex: add namespace lookup support
llvm-svn: 334186
2018-06-07 10:56:16 +00:00
Pavel Labath 452bd87cc4 DebugNamesDWARFIndex: Add support for partial indexes
Summary:
It possible that a single module has indexed and non-indexed compile
units. In this case, we can use the fast indexed lookup for the first
ones and fall back to the manual index for the others.

This patch implements this functionality by adding a units_to_avoid
argument to the ManualDWARFIndex constructor. Any units present in that
list will be ignored for the purposes of manual index. Individual
DebugNamesDWARFIndex then always consult both the manual fallback index
as well as the index in the .debug_names section.

Reviewers: JDevlieghere, clayborg

Subscribers: aprantl, lldb-commits

Differential Revision: https://reviews.llvm.org/D47832

llvm-svn: 334185
2018-06-07 10:35:28 +00:00
Matt Arsenault 697300bd4f AMDGPU: Use scalar operations for f16 fabs/fneg patterns
Fixes unnecessary differences between subtargets.

llvm-svn: 334184
2018-06-07 10:15:20 +00:00
Simon Pilgrim cc92897be9 [X86] Regenerate rotate tests
Add 32-bit tests to show missed SHLD/SHRD cases

llvm-svn: 334183
2018-06-07 10:13:09 +00:00
Paul Semel e57bc78324 [llvm-strip] Expose --strip-unneeded option
Differential Revision: https://reviews.llvm.org/D47818

llvm-svn: 334182
2018-06-07 10:05:25 +00:00
Pavel Labath e1d18758eb DebugNamesDWARFIndex: Add ability to lookup variables
Summary:
This patch adds the ability to lookup variables to the DWARF v5 index
class.

During review we discovered an inconsistency between how the existing
two indexes handle looking up qualified names of the variables:
- manual index would return a value if the input string exactly matched
  the demangled name of some variable.
- apple index ignored the context and returned any variable with the
  same base name.

So, this patch also rectifies that situation:
- it removes all context handling from the index classes. The
  GetGlobalVariables functions now just take a base name. For manual
  index, this meant we can stop putting demangled names into the
  variable index (this matches the behavior for functions).
- context extraction is put into SymbolFileDWARF, so that it is common
  to all indexes.
- additional filtering based on the context is also done in
  SymbolFileDWARF. This is done via a simple substring search, which is
  not ideal, but it matches what we are doing for functions (cf.
  Module::LookupInfo::Prune).

Reviewers: clayborg, JDevlieghere

Subscribers: aprantl, lldb-commits

Differential Revision: https://reviews.llvm.org/D47781

llvm-svn: 334181
2018-06-07 10:04:44 +00:00
Matt Arsenault 90083d3088 AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.

The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.

When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.

There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.

Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.

Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.

The use of the  scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.

llvm-svn: 334180
2018-06-07 09:54:49 +00:00
Krasimir Georgiev 45dde418a9 [clang-format] Consider tok::hashhash in python-style comments
Summary: We were missing the case when python-style comments in text protos start with `##`.

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D47870

llvm-svn: 334179
2018-06-07 09:46:24 +00:00
Clement Courbet 4281b1d3b5 [X86][NFC] Fix harmless typo in BtVer2 model.
See D46356 for context.

llvm-svn: 334178
2018-06-07 09:26:33 +00:00
David Carlier 58d05a4d5f [LLDB] Unit tests / typo fix
removing unnecessary comma.

llvm-svn: 334177
2018-06-07 08:58:34 +00:00
Haojian Wu 6138b78672 [clangd] Fix using the incorrect Index for go-to-definition.
Reviewers: sammccall

Subscribers: ilya-biryukov, ioeric, MaskRay, jkorous, cfe-commits

Differential Revision: https://reviews.llvm.org/D47869

llvm-svn: 334176
2018-06-07 08:49:55 +00:00
Tomasz Krupa f8c7637027 [X86] Block UndefRegUpdate
Summary: Prevent folding of operations with memory loads when one of the sources has undefined register update.

Reviewers: craig.topper

Subscribers: llvm-commits, mike.dvoretsky, ashlykov

Differential Revision: https://reviews.llvm.org/D47621

llvm-svn: 334175
2018-06-07 08:48:45 +00:00
Gabor Buella 1a83d06768 [CodeGen] Improve diagnostics related to target attributes
Summary:
When requirement imposed by __target__ attributes on functions
are not satisfied, prefer printing those requirements, which
are explicitly mentioned in the attributes.

This makes such messages more useful, e.g. printing avx512f instead of avx2
in the following scenario:

```
$ cat foo.c
static inline void __attribute__((__always_inline__, __target__("avx512f")))
x(void)
{
}

int main(void)
{
            x();
}
$ clang foo.c
foo.c:7:2: error: always_inline function 'x' requires target feature 'avx2', but would be inlined into function 'main' that is compiled without support for 'avx2'
        x();
    ^
1 error generated.
```

bugzilla: https://bugs.llvm.org/show_bug.cgi?id=37338

Reviewers: craig.topper, echristo, dblaikie

Reviewed By: craig.topper, echristo

Differential Revision: https://reviews.llvm.org/D46541

llvm-svn: 334174
2018-06-07 08:48:36 +00:00
Max Kazantsev b4b2ccea6d [NFC] Use variable instead of accessing pair many times
llvm-svn: 334173
2018-06-07 08:47:19 +00:00
Philip Pfaffe e6e1828004 Run clang-format
llvm-svn: 334172
2018-06-07 08:32:13 +00:00
Tomasz Krupa 145825162a Test commit access.
Added a bunch of periods after comments.

llvm-svn: 334171
2018-06-07 08:20:28 +00:00
Sam McCall c22c9aa414 [clangd] fix unintended fallthrough in scope-based scoring
llvm-svn: 334170
2018-06-07 08:16:36 +00:00
Guillaume Chatelet 7b852cd814 [llvm-exegesis] Add a Configuration object for Benchmark.
Summary: This is the first step to have the BenchmarkRunner create and measure many different configurations (different initial values for instance).

Reviewers: courbet

Subscribers: tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D47826

llvm-svn: 334169
2018-06-07 08:11:54 +00:00
Kamil Rytarowski b9c78e41ba Disable recursive interceptors in signal(3)/MSan
Summary:
signal(3) on NetBSD calls internally sigaction(2).

Without disabling the recursive interceptor, there are
false positives about uninitialized memory reads inside libc.

This change fixes execution of such programs as sh(1) and
vmstat(1) in the NetBSD userland.

Sponsored by <The NetBSD Foundation>

Reviewers: eugenis, vitalybuka, joerg

Reviewed By: vitalybuka

Subscribers: llvm-commits, #sanitizers

Tags: #sanitizers

Differential Revision: https://reviews.llvm.org/D47650

llvm-svn: 334168
2018-06-07 07:55:20 +00:00
Guillaume Chatelet 8c91d4cb04 [llvm-exegesis] Improve error reporting.
Summary: BenchmarkResult IO functions now return an Error or Expected so caller can deal take proper action.

Reviewers: courbet

Subscribers: tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D47868

llvm-svn: 334167
2018-06-07 07:51:16 +00:00
Philip Pfaffe 30c5e4ad35 Fix a missing lambda return type that tripped the builders
llvm-svn: 334166
2018-06-07 07:50:55 +00:00
Guillaume Chatelet 083a0c1621 [llvm-exegesis] Serializes instruction's operand in BenchmarkResult's key.
Summary: Follow up patch to https://reviews.llvm.org/D47764.

Reviewers: courbet

Subscribers: tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D47785

llvm-svn: 334165
2018-06-07 07:40:40 +00:00
Clement Courbet 9212ef0a0a [X86][NFC] Fix harmless typos in BDW/ZnVer1 sched models.
See D46356 for context.

llvm-svn: 334164
2018-06-07 07:37:49 +00:00
Karl-Johan Karlsson abb11f805f [BranchFolding] Fix live-in's when hoisting code
Summary:
When the branch folder hoist code into a predecessor it adjust live-in's
in the blocks it hoist code from. However it fail to handle hoisted code
that contain a defed register that originally is live-in in the block
through a super register.

This is fixed by replacing the live-in handling code with calls to
utility functions in LivePhysRegs.

Reviewers: kparzysz, gberry, MatzeB, uweigand, aprantl

Reviewed By: kparzysz

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D47529

llvm-svn: 334163
2018-06-07 07:20:33 +00:00
Sam McCall 203cdee0ec [clangd] Make workspace/symbols actually rank its results.
Summary: The index doesn't actually return results in ranked order.

Reviewers: hokein

Subscribers: ilya-biryukov, ioeric, MaskRay, jkorous, cfe-commits

Differential Revision: https://reviews.llvm.org/D47821

llvm-svn: 334162
2018-06-07 06:55:59 +00:00
Jonas Paulsson e80d405760 [SystemZ] Build Load And Test from scratch in convertToLoadAndTest.
This is needed to get CC operand in right place, as expected by the
SchedModel.

Review: Ulrich Weigand
https://reviews.llvm.org/D47820

llvm-svn: 334161
2018-06-07 05:59:07 +00:00
Richard Trieu 8153628f6a Change return value of trivial visibility check.
Previous, if no Decl's were checked, visibility was set to false.  Switch it
so that in cases of no Decl's, return true.  These are the Decl's after being
filtered.  Also remove an unreachable return statement since it is directly
after another return statement.

llvm-svn: 334160
2018-06-07 03:20:30 +00:00
Craig Topper b92c77d176 [X86] Add back _mask, _maskz, and _mask3 builtins for some 512-bit fmadd/fmsub/fmaddsub/fmsubadd builtins.
Summary:
We recently switch to using a selects in the intrinsics header files for FMA instructions. But the 512-bit versions support flavors with rounding mode which must be an Integer Constant Expression. This has forced those intrinsics to be implemented as macros. As it stands now the mask and mask3 intrinsics evaluate one of their macro arguments twice. If that argument itself is another intrinsic macro, we can end up over expanding macros. Or if its something we can CSE later it would show up multiple times when it shouldn't.

I tried adding __extension__ around the macro and making it an expression statement and declaring a local variable. But whatever name you choose for the local variable can never be used as the name of an input to the macro in user code. If that happens you would end up with the same name on the LHS and RHS of an assignment after expansion. We might be safe if we use __ in front of the variable names because those names are reserved and user code shouldn't use that, but I wasn't sure I wanted to make that claim.

The other option which I've chosen here, is to add back _mask, _maskz, and _mask3 flavors of the builtin which we will expand in CGBuiltin.cpp to replicate the argument as needed and insert any fneg needed on the third operand to make a subtract. The _maskz isn't truly necessary if we have an unmasked version or if we use the masked version with a -1 mask and wrap a select around it. But I've chosen to make things more uniform.

I separated out the scalar builtin handling to avoid too many things going on in EmitX86FMAExpr. It was different enough due to the extract and insert that the minor duplication of the CreateCall was probably worth it.

Reviewers: tkrupa, RKSimon, spatel, GBuella

Reviewed By: tkrupa

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D47724

llvm-svn: 334159
2018-06-07 02:46:02 +00:00
Kostya Serebryany 67af99235f [libFuzzer] make the corpus elements aware of their data flow traces
llvm-svn: 334158
2018-06-07 01:40:20 +00:00
Sam Clegg 177b458c8a [WebAssembly] Add --export-all flag
This causes all symbols to be exported in the final wasm binary
even if they were not compiled with default visibility.

This feature is useful for the emscripten toolchain that has a
corresponding EXPORT_ALL feature which allows the JS code to
interact with all C function.

Differential Revision: https://reviews.llvm.org/D47806

llvm-svn: 334157
2018-06-07 01:27:07 +00:00
Kostya Serebryany 7a88f19099 [libFuzzer] simplify a test, hopefully to fix the bot
llvm-svn: 334156
2018-06-07 01:18:43 +00:00
Han Shen 7452f73c43 ClangTidy fix - 'clang::Sema::checkAllowedCUDAInitializer' has a definition with different parameter names.
llvm-svn: 334155
2018-06-07 00:55:54 +00:00
Bob Haarman 30913ac39d [COFF] report file containing unsupported relocation
Summary:
When reporting an unsupported relocation type, let's also report the
file we encountered it in to aid diagnosis.

Reviewers: ruiu, rnk

Reviewed By: rnk

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45911

llvm-svn: 334154
2018-06-07 00:50:03 +00:00
Sunil Srivastava a74031b640 Change the wording of RTTI errors to make them more generic.
An attempt to use dynamic_cast while rtti is disabled, used to emit the error:

  cannot use dynamic_cast with -fno-rtti

and a similar one for typeid.

This patch changes that to:

  use of dynamic_cast requires -frtti

Differential Revision: https://reviews.llvm.org/D47291

llvm-svn: 334153
2018-06-07 00:42:59 +00:00