Commit Graph

25629 Commits

Author SHA1 Message Date
Richard Sandiford d816320809 [SystemZ] Use getTarget{Insert,Extract}Subreg rather than getMachineNode
Just a clean-up, no behavioral change intended.

llvm-svn: 190673
2013-09-13 09:12:44 +00:00
Richard Sandiford 030c165710 [SystemZ] Try to fold shifts into TMxx
E.g. "SRL %r2, 2; TMLL %r2, 1" => "TMLL %r2, 4".

llvm-svn: 190672
2013-09-13 09:09:50 +00:00
Tim Northover 635a979038 AArch64: use RegisterOperand for NEON registers.
Previously we modelled VPR128 and VPR64 as essentially identical
register-classes containing V0-V31 (which had Q0-Q31 as "sub_alias"
sub-registers). This model is starting to cause significant problems
for code generation, particularly writing EXTRACT/INSERT_SUBREG
patterns for converting between the two.

The change here switches to classifying VPR64 & VPR128 as
RegisterOperands, which are essentially aliases for RegisterClasses
with different parsing and printing behaviour. This fits almost
exactly with their real status (VPR128 == FPR128 printed strangely,
VPR64 == FPR64 printed strangely).

llvm-svn: 190665
2013-09-13 07:26:52 +00:00
Craig Topper 21a916b6db Move operator to end of previous line to match coding standards.
llvm-svn: 190659
2013-09-13 04:41:06 +00:00
Vincent Lejeune 0167a313da R600: Move clamp handling code to R600IselLowering.cpp
llvm-svn: 190645
2013-09-12 23:45:00 +00:00
Vincent Lejeune 9a248e5c2d R600: Move code handling literal folding into R600ISelLowering.
llvm-svn: 190644
2013-09-12 23:44:53 +00:00
Vincent Lejeune ab3baf80a8 R600: Move fabs/fneg/sel folding logic into PostProcessIsel
This move makes possible to correctly handle multiples instructions
from a single pattern.

llvm-svn: 190643
2013-09-12 23:44:44 +00:00
Chandler Carruth 51428e363f Remove an unused variable, fixing -Werror build with latest Clang.
llvm-svn: 190640
2013-09-12 23:30:48 +00:00
Hal Finkel 262a224712 Fix PPC ABI for ByVal structs with vector members
When a structure is passed by value, and that structure contains a vector
member, according to the PPC ABI, the structure will receive enhanced alignment
(so that the vector within the structure will always be aligned).

This should resolve PR16641.

llvm-svn: 190636
2013-09-12 23:20:06 +00:00
Hal Finkel 1e2e3ea584 Make the PPC fast-math sqrt expansion safe at 0
In fast-math mode sqrt(x) is calculated using the fast expansion of the
reciprocal of the reciprocal sqrt expansion. The reciprocal and reciprocal
sqrt expansions use the associated estimate instructions along with some Newton
iterations. Unfortunately, as a result, sqrt(0) was being calculated as NaN,
which is not correct. Now we explicitly return a result of zero if the input is
zero.

llvm-svn: 190624
2013-09-12 19:04:12 +00:00
Roman Divacky 62cb63543b Implement asm support for a few PowerPC bookIII that are needed for assembling
FreeBSD kernel.

llvm-svn: 190618
2013-09-12 17:50:54 +00:00
Ben Langmuir 1650175de6 Partial support for Intel SHA Extensions (sha1rnds4)
Add basic assembly/disassembly support for the first Intel SHA
instruction 'sha1rnds4'. Also includes feature flag, and test cases.

Support for the remaining instructions will follow in a separate patch.

llvm-svn: 190611
2013-09-12 15:51:31 +00:00
Hal Finkel 0096dbd50d Mark PPC MFTB and DST (and friends) as deprecated
Use the new instruction deprecation feature to mark mftb (now replaced with
mfspr) and dst (along with the other Altivec cache control instructions) as
deprecated when targeting cores supporting at least ISA v2.03.

llvm-svn: 190605
2013-09-12 14:40:06 +00:00
Joey Gouly 0e76fa7df5 Add an instruction deprecation feature to TableGen.
The 'Deprecated' class allows you to specify a SubtargetFeature that the
instruction is deprecated on.

The 'ComplexDeprecationPredicate' class allows you to define a custom
predicate that is called to check for deprecation.
For example:
  ComplexDeprecationPredicate<"MCR">

would mean you would have to define the following function:
  bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
                             std::string &Info)

Which returns 'false' for not deprecated, and 'true' for deprecated
and store the warning message in 'Info'.

The MCTargetAsmParser constructor was chaned to take an extra argument of
the MCInstrInfo class, so out-of-tree targets will need to be changed.

llvm-svn: 190598
2013-09-12 10:28:05 +00:00
Elena Demikhovsky 8952974e29 AVX-512: implemented extractelement with variable index.
Added parsing of mask register and "zeroing" semantic, like {%k1} {z}.

llvm-svn: 190595
2013-09-12 08:55:00 +00:00
Hal Finkel 7fe6a5390f PPC: Enable aggressive anti-dependency breaking
Aggressive anti-dependency breaking is enabled by default for all PPC cores.
This provides a general speedup on the P7 and other platforms (among other
factors, the instruction group formation for the non-embedded PPC cores is done
during post-RA scheduling). In order to do this safely, the incompatibility
between uses of the MFOCRF instruction and anti-dependency breaking are
resolved by marking MFOCRF with hasExtraSrcRegAllocReq. As noted in the removed
FIXME, the problem was that MFOCRF's output is sensitive to the identify of the
source register, and always paired with a shift to undo this effect. Because
anti-dependency breaking is unaware of this hidden dependency of the shift
amount on the source register of the MFOCRF instruction, changing that register
must be inhibited.

Two test cases were adjusted: The SjLj test was made more insensitive to
register choices and scheduling; the saveCR test disabled anti-dependency
breaking because part of what it is testing is proper register reuse.

llvm-svn: 190587
2013-09-12 05:24:49 +00:00
Tom Stellard afcf12f33a R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback
For _XYZ, the type of VDATA is v4i32, because v3i32 doesn't exist.

The ADDR64 bit is not exposed. A simpler intrinsic that doesn't take
a resource descriptor might be nicer.

The maximum number of input SGPRs is bumped to 17.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 190575
2013-09-12 02:55:14 +00:00
Tom Stellard 7f6fa4c4c5 R600: Don't use trans slot for instructions that read LDS source registers
This fixes some regressions in the piglit local memory store tests
introduced by recent commits which made the scheduler aware of the trans
slot.

It's not possible to test this using lit, because there is no way to
determine from the assembly dumps whether or not an instruction is in
the trans slot.

Even if this were possible, the test would be highly sensitive to
changes in the scheduler and might generate confusing false negatives.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 190574
2013-09-12 02:55:06 +00:00
Hal Finkel f574c27769 Greatly simplify the PPC A2 scheduling itinerary
As Andy pointed out to me a long time ago, there are no structural hazards in
the later pipeline stages of the A2, and so modeling them is useless. Also,
modeling the top pre-dispatch stages is deceiving because, when multiple
hardware threads are active, those resources are shared among the threads. The
bypass definitions were mostly wrong, and so those have been removed. The
resulting itinerary is much simpler, and more accurate.

llvm-svn: 190562
2013-09-11 23:25:21 +00:00
Hal Finkel 21442b24fb Enable MI scheduling (and CodeGen AA) by default for embedded PPC cores
For embedded PPC cores (especially the A2 core), using the MI scheduler with AA
is far superior to the other scheduling options.

llvm-svn: 190558
2013-09-11 23:05:25 +00:00
Bill Wendling 7b650a751f Use the appropriate return type for the compact unwind encoding.
llvm-svn: 190551
2013-09-11 21:47:57 +00:00
Hal Finkel 71780ec4fd Implement TTI getUnrollingPreferences for PowerPC
The PowerPC A2 core greatly benefits from aggressive concatenation unrolling;
use the new getUnrollingPreferences to enable this by default when targeting
the PPC A2 core.

llvm-svn: 190549
2013-09-11 21:20:40 +00:00
Bill Wendling 184d5d31bc Move into an anonymous namespace and closer to where it's used.
llvm-svn: 190547
2013-09-11 20:38:09 +00:00
Daniel Sanders fbcb582942 [mips][msa] Added support for matching mulv, nlzc, sll, sra, srl, and subv from normal IR (i.e. not intrinsics)
llvm-svn: 190518
2013-09-11 11:58:30 +00:00
Daniel Sanders f5bd937bc4 [mips][msa] Added support for matching fadd, fdiv, flog2, fmul, frint, fsqrt, and fsub from normal IR (i.e. not intrinsics)
llvm-svn: 190512
2013-09-11 10:51:30 +00:00
Daniel Sanders 607952bdad [mips][msa] Added support for matching div_[su] from normal IR (i.e. not intrinsics)
llvm-svn: 190509
2013-09-11 10:38:58 +00:00
Daniel Sanders fa5ab1c856 [mips][msa] Added support for matching addv from normal IR (i.e. not intrinsics)
The corresponding intrinsic is now lowered into equivalent IR (ISD::ADD) before instruction selection.

llvm-svn: 190507
2013-09-11 10:28:16 +00:00
Daniel Sanders c65f58a9c7 [mips][msa] Separate the configuration of int/float vector types since they will diverge soon
No functional change

llvm-svn: 190506
2013-09-11 10:15:48 +00:00
Daniel Sanders cb2929c239 [mips][msa] Corrected the definition of the dotp_[su].[hwd] intrinsics
The elements of the operands should be half the width of the elements of
the result.

llvm-svn: 190505
2013-09-11 09:59:17 +00:00
Eli Friedman 8f06d55697 Rename variables for consistency.
No functional change.

llvm-svn: 190466
2013-09-11 00:41:02 +00:00
Eli Friedman 78bffa5767 Fix unused variables.
llvm-svn: 190448
2013-09-10 23:18:14 +00:00
Eli Friedman 1891f69323 Remove unused functions.
llvm-svn: 190442
2013-09-10 22:42:31 +00:00
Jim Grosbach 19ae779af1 ARM: Use the PICADD opcode calculated.
We were figuring out whether to use tPICADD or PICADD, then just using
tPICADD unconditionally anyway. Oops.

A testcase from someone familiar enough with ELF to produce one would
be appreciated. The existing PIC testcase correctly verifies the .s
generated, but that doesn't catch this bug, which only showed up in
direct-to-object mode.

http://llvm.org/bugs/show_bug.cgi?id=17180

llvm-svn: 190417
2013-09-10 17:21:39 +00:00
Logan Chien d532cb6bed Remove unused private member in ARMAsmPrinter.cpp.
This commit removes the unused "AttributeItem" from
ObjectAttributeEmitter.

llvm-svn: 190412
2013-09-10 15:10:02 +00:00
Richard Sandiford 0e0498b288 [SystemZ] Update README.
llvm-svn: 190404
2013-09-10 12:22:45 +00:00
Richard Sandiford a9eb9972e4 [SystemZ] Add TM and TMY
The main complication here is that TM and TMY (the memory forms) set
CC differently from the register forms.  When the tested bits contain
some 0s and some 1s, the register forms set CC to 1 or 2 based on the
value the uppermost bit.  The memory forms instead set CC to 1
regardless of the uppermost bit.

Until now, I've tried to make it so that a branch never tests for an
impossible CC value.  E.g. NR only sets CC to 0 or 1, so branches on the
result will only test for 0 or 1.  Originally I'd tried to do the same
thing for TM and TMY by using custom matching code in ISelDAGToDAG.
That ended up being very ugly though, and would have meant duplicating
some of the chain checks that the common isel code does.

I've therefore gone for the simpler alternative of adding an extra
operand to the TM DAG opcode to say whether a memory form would be OK.
This means that the inverse of a "TM;JE" is "TM;JNE" rather than the
more precise "TM;JNLE", just like the inverse of "TMLL;JE" is "TMLL;JNE".
I suppose that's arguably less confusing though...

llvm-svn: 190400
2013-09-10 10:20:32 +00:00
Daniel Sanders f561730af8 [mips][msa] Removed unsupported dot product instructions (dotp_[su].b)
The dotp_[su].b instructions never existed in any revision of the MSA spec.

llvm-svn: 190398
2013-09-10 09:51:43 +00:00
Vladimir Medic 65cd57445e Add test cases for Mips mthc1/mfhc1 instructions. Add check for odd value of register when PFU is 32 bit.
llvm-svn: 190397
2013-09-10 09:50:01 +00:00
Vladimir Medic 8826970632 Remove obsolete code from MipsAsmParser.cpp.
llvm-svn: 190396
2013-09-10 09:39:55 +00:00
Bill Wendling f27e331510 Revert r190366. It was breaking build bots.
llvm-svn: 190373
2013-09-10 00:20:27 +00:00
Bill Wendling b07305fcd4 Use a default value for the prologue's debug location.
llvm-svn: 190366
2013-09-09 23:28:15 +00:00
Bob Wilson e407736a06 Revert patches to add case-range support for PR1255.
The work on this project was left in an unfinished and inconsistent state.
Hopefully someone will eventually get a chance to implement this feature, but
in the meantime, it is better to put things back the way the were.  I have
left support in the bitcode reader to handle the case-range bitcode format,
so that we do not lose bitcode compatibility with the llvm 3.3 release.

This reverts the following commits: 155464, 156374, 156377, 156613, 156704,
156757, 156804 156808, 156985, 157046, 157112, 157183, 157315, 157384, 157575,
157576, 157586, 157612, 157810, 157814, 157815, 157880, 157881, 157882, 157884,
157887, 157901, 158979, 157987, 157989, 158986, 158997, 159076, 159101, 159100,
159200, 159201, 159207, 159527, 159532, 159540, 159583, 159618, 159658, 159659,
159660, 159661, 159703, 159704, 160076, 167356, 172025, 186736

llvm-svn: 190328
2013-09-09 19:14:35 +00:00
Akira Hatanaka 9cf069f60a [mips] When double precision loads and stores are split into two i32 loads and
stores, make sure the load or store that accesses the higher half does not have
an alignment that is larger than the offset from the original address.

llvm-svn: 190318
2013-09-09 17:59:32 +00:00
Joey Gouly a5153cb025 [ARMv8] Prevent generation of deprecated IT blocks on ARMv8 in Thumb mode.
IT blocks can only be one instruction lonf, and can only contain a subset of
the 16 instructions.

Patch by Artyom Skrobov!

llvm-svn: 190309
2013-09-09 14:21:49 +00:00
Aaron Ballman 83d81784df A better way to silence the warning in MSVC (replaces r190304).
llvm-svn: 190308
2013-09-09 14:17:30 +00:00
Aaron Ballman c4280dd977 Silencing a warning about control flow reaching the end of a non-void function.
llvm-svn: 190304
2013-09-09 13:22:45 +00:00
Robert Lytton 3d3194bf06 XCore handling of thread local lowering
Fix XCoreLowerThreadLocal trying to initialise globals
which have no initializer.

Add handling of const expressions containing thread local variables.
These need to be replaced with instructions, as the thread ID is
used to access the thread local variable.

llvm-svn: 190300
2013-09-09 10:42:11 +00:00
Robert Lytton 4809ea41e6 XCore target: change to Sched::Source
This sidesteps a bug in PrescheduleNodesWithMultipleUses() which
does not check if callResources will be affected by the transformation.

llvm-svn: 190299
2013-09-09 10:42:05 +00:00
Robert Lytton e453888379 XCore target: fix weak linkage attribute handling
llvm-svn: 190298
2013-09-09 10:41:57 +00:00
Bill Wendling 58e2d3d856 Generate compact unwind encoding from CFI directives.
We used to generate the compact unwind encoding from the machine
instructions. However, this had the problem that if the user used `-save-temps'
or compiled their hand-written `.s' file (with CFI directives), we wouldn't
generate the compact unwind encoding.

Move the algorithm that generates the compact unwind encoding into the
MCAsmBackend. This way we can generate the encoding whether the code is from a
`.ll' or `.s' file.

<rdar://problem/13623355>

llvm-svn: 190290
2013-09-09 02:37:14 +00:00
Jiangning Liu 2878dc8fe7 Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the following 26 instructions,
SADDL, UADDL, SADDW, UADDW, SSUBL, USUBL, SSUBW, USUBW, ADDHN, RADDHN, SABAL, UABAL, SUBHN, RSUBHN, SABDL, UABDL, SMLAL, UMLAL, SMLSL, UMLSL, SQDMLAL, SQDMLSL, SMULL, UMULL, SQDMULL, PMULL

llvm-svn: 190288
2013-09-09 02:20:27 +00:00
Craig Topper adbb9a121f Add neverHasSideEffects=1 on a couple move instructions.
llvm-svn: 190259
2013-09-08 00:50:45 +00:00
Craig Topper 0a63e1da92 Using popcount should check the popcount feature flag not the SSE41 feature flag.
llvm-svn: 190258
2013-09-08 00:47:31 +00:00
Akira Hatanaka 6379121694 [mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double
precision loads and stores as well as reg+imm double precision loads and stores.

Previously, expansion of loads and stores was done after register allocation,
but now it takes place during legalization. As a result, users will see double
precision stores and loads being emitted to spill and restore 64-bit FP registers.

llvm-svn: 190235
2013-09-07 00:52:30 +00:00
Akira Hatanaka 92ec3bd50b [mips] Place parentheses around && to silence warning.
llvm-svn: 190234
2013-09-07 00:26:26 +00:00
Akira Hatanaka 6a3fe57444 [mips] Add definition of instruction "drotr32" (double rotate right plus 32).
llvm-svn: 190232
2013-09-07 00:18:01 +00:00
Akira Hatanaka 3121353c99 [mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit
into a 5-bit or 6-bit field.

llvm-svn: 190226
2013-09-07 00:02:02 +00:00
Akira Hatanaka 79e38cde37 [mips] Define "trap" as a pseudo instruction that turns into "break 0, 0".
llvm-svn: 190224
2013-09-06 23:52:46 +00:00
Akira Hatanaka 50eebac68b [mips] Delete unused classes and defs.
llvm-svn: 190221
2013-09-06 23:42:58 +00:00
Akira Hatanaka 2c544d8ed5 [mips] Make "b" (unconditional branch) a pseudo. "b" is an assembly idiom, which is
equivalent to "beq $zero, $zero, offset".

llvm-svn: 190220
2013-09-06 23:40:15 +00:00
Akira Hatanaka dffc542123 [mips] Set instruction itineraries of loads, stores and conditional moves.
llvm-svn: 190219
2013-09-06 23:28:24 +00:00
Aaron Watry 372cecf642 R600: Add support for LDS atomic subtract
Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 190200
2013-09-06 20:17:42 +00:00
Daniel Sanders af7f805b96 [mips][msa] Indentation
llvm-svn: 190156
2013-09-06 13:25:06 +00:00
Daniel Sanders 636f72fc08 [mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance
Tested with 'llvm-tblgen -print-records' which outputs identical records before
and after this patch.

llvm-svn: 190155
2013-09-06 13:15:05 +00:00
Vladimir Medic b936da159e This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.
llvm-svn: 190154
2013-09-06 13:08:00 +00:00
Daniel Sanders 563e5eabe5 [mips][msa] Made the operand register sets optional for the VEC formats
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190153
2013-09-06 13:01:47 +00:00
Vladimir Medic 457ba56b05 This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch.
llvm-svn: 190152
2013-09-06 12:53:21 +00:00
Daniel Sanders 41fb2c0d0e [mips][msa] Made the operand register sets optional for the ELM_INSVE formats
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190151
2013-09-06 12:50:52 +00:00
Daniel Sanders fa1b0fa77e [mips][msa] Made the operand register sets optional for the 3RF_4RF format
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190150
2013-09-06 12:44:13 +00:00
Vladimir Medic e0fbb44a48 This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch.
llvm-svn: 190148
2013-09-06 12:41:17 +00:00
Daniel Sanders d719f5281c [mips][msa] Made the operand register sets optional for the 3RF formats
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190146
2013-09-06 12:32:57 +00:00
Daniel Sanders b2b7c0a044 [mips][msa] Made the operand register sets optional for the 3R_4R format
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190145
2013-09-06 12:30:43 +00:00
Vladimir Medic dde3d582a2 This patch adds support for microMIPS disassembler and disassembler make check tests.
llvm-svn: 190144
2013-09-06 12:30:36 +00:00
Daniel Sanders 2322f5d090 [mips][msa] Made the operand register sets optional for the 2RF format
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190143
2013-09-06 12:28:13 +00:00
Daniel Sanders 9148218cbe [mips][msa] Made the operand register sets optional for the I8 format
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190142
2013-09-06 12:25:47 +00:00
Daniel Sanders 92c40a5796 [mips][msa] Made the operand register sets optional for the I5 and SI5 formats
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190141
2013-09-06 12:23:19 +00:00
Daniel Sanders 13d5e2f376 [mips][msa] Made the operand register sets optional for the BIT_[BHWD] formats
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190140
2013-09-06 12:10:24 +00:00
Richard Sandiford 5bc670bb55 [SystemZ] Tweak integer comparison code
The architecture has many comparison instructions, including some that
extend one of the operands.  The signed comparison instructions use sign
extensions and the unsigned comparison instructions use zero extensions.
In cases where we had a free choice between signed or unsigned comparisons,
we were trying to decide at lowering time which would best fit the available
instructions, taking things like extension type into account.  The code
to do that was getting increasingly hairy and was also making some bad
decisions.  E.g. when comparing the result of two LLCs, it is better to use
CR rather than CLR, since CR can be fused with a branch while CLR can't.

This patch removes the lowering code and instead adds an operand to
integer comparisons to say whether signed comparison is required,
whether unsigned comparison is required, or whether either is OK.
We can then leave the choice of instruction up to the normal isel code.

llvm-svn: 190138
2013-09-06 11:51:39 +00:00
Daniel Sanders 63b97d5ae5 [mips][msa] Sorted MSA_BIT_[BHWD]_DESC_BASE into ascending order of element size
No functional change

llvm-svn: 190134
2013-09-06 11:01:38 +00:00
Daniel Sanders 02a3007608 [mips][msa] Made the operand register sets optional for the 3R format
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190133
2013-09-06 10:59:24 +00:00
Daniel Sanders db12ab7b7c [mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment.
No functional change

llvm-svn: 190131
2013-09-06 10:55:15 +00:00
Richard Sandiford 4943bc393a [SystemZ] Use XC for a memset of 0
llvm-svn: 190130
2013-09-06 10:25:07 +00:00
Tom Stellard 8bc633ac09 R600: Coding style
llvm-svn: 190110
2013-09-05 23:55:13 +00:00
Juergen Ributzka 53d0b492f5 [X86] Perform VSELECT DAG combines also before DAG type legalization.
If the DAG already has only legal types, then the second round of DAG combines
is skipped. In this case VSELECT+SETCC patterns that match a more efficient
instruction (e.g. min/max) are never recognized.

This fix allows VSELECT+SETCC combines if the types are already legal before DAG
type legalization.

Reviewer: Nadav
llvm-svn: 190105
2013-09-05 23:02:56 +00:00
Kevin Enderby 09cdb4385f Fixed a crash in the integrated assembler for Mach-O when a symbol difference
expression uses an assembler temporary symbol from an assignment.  In this case
the symbol does not have a fragment so the use of getFragment() would be NULL
and caused a crash. In the case of an assembler temporary symbol we want to use
the AliasedSymbol (if any) which will create a local relocation entry, but if
it is not an assembler temporary symbol then let it use that symbol with an
external relocation entry.

rdar://9356266

llvm-svn: 190096
2013-09-05 20:25:06 +00:00
Matt Arsenault 6f24379974 R600: Fix i64 to i32 trunc on SI
llvm-svn: 190091
2013-09-05 19:41:10 +00:00
Tom Stellard 13c68ef88b R600: Add support for local memory atomic add
llvm-svn: 190080
2013-09-05 18:38:09 +00:00
Tom Stellard 53f2f90eb4 R600: Expand SELECT nodes rather than custom lowering them
llvm-svn: 190079
2013-09-05 18:38:03 +00:00
Tom Stellard de60e25278 R600: Fix incorrect LDS size calculation
GlobalAdderss nodes that appeared in more than one basic block were
being counted twice.

llvm-svn: 190078
2013-09-05 18:37:57 +00:00
Tom Stellard d50bb3c8d4 R600/SI: Don't emit S_WQM_B64 instruction for compute shaders
llvm-svn: 190077
2013-09-05 18:37:52 +00:00
Tom Stellard 624741fded R600: Fix segfault in R600TextureIntrinsicReplacer
This pass was segfaulting when it ran into a non-intrinsic function
call.  Function calls are not supported, so now instead of segfaulting,
we will get an assertion failure with a nice error message.

I'm not sure how to test this using lit.

llvm-svn: 190076
2013-09-05 18:37:45 +00:00
Joey Gouly 926d3f5809 [ARMv8] Implement the new DMB/DSB operands.
This removes the custom ISD Node: MEMBARRIER and replaces it
with an intrinsic.

llvm-svn: 190055
2013-09-05 15:35:24 +00:00
Richard Barton 8d519fe015 Add AArch32 DCPS{1,2,3} and HLT instructions.
These were pretty straightforward instructions, with some assembly support
required for HLT.

The ARM assembler is keen to split the instruction mnemonic into a
(non-existent) 'H' instruction with the LT condition code. An exception for
HLT is needed.

HLT follows the same rules as BKPT when in IT blocks, so the special BKPT
hadling code has been adapted to handle HLT also.

Regression tests added including diagnostic tests for out of range immediates
and illegal condition codes, as well as negative tests for pre-ARMv8.

llvm-svn: 190053
2013-09-05 14:14:19 +00:00
Tilmann Scheller 841a9ccfed Reverting 190043 for now.
Solution is not sufficient to prevent 'mov pc, lr' being emitted for jump table code.
Test case doesn't trigger the added functionality.

llvm-svn: 190047
2013-09-05 11:59:43 +00:00
Tilmann Scheller a1787a5835 ARM: Add GPR register class excluding LR for use with the ADR instruction.
This improves code generation for jump tables by avoiding the emission of "mov pc, lr" which could fool the processor into believing this is a return from a function causing mispredicts. The code generation logic for jump tables uses ADR to materialize the address of the jump target.

Patch by Daniel Stewart!
   

llvm-svn: 190043
2013-09-05 11:10:31 +00:00
Richard Sandiford 178273a174 [SystemZ] Add NC, OC and XC
For now these are just used to handle scalar ANDs, ORs and XORs in which
all operands are memory.

llvm-svn: 190041
2013-09-05 10:36:45 +00:00
Venkatraman Govindaraju 55ecb10e99 [Sparc] Correctly handle call to functions with ReturnsTwice attribute.
In sparc, setjmp stores only the registers %fp, %sp, %i7 and %o7. longjmp restores
the stack, and the callee-saved registers (all local/in registers: %i0-%i7, %l0-%l7)
using the stored %fp and register windows. However, this does not guarantee that the longjmp
will restore the registers, as they were when the setjmp was called. This is because these
registers may be clobbered after returning from setjmp, but before calling longjmp.

This patch prevents the registers %i0-%i5, %l0-l7 to live across the setjmp call using the register mask.  

llvm-svn: 190033
2013-09-05 05:32:16 +00:00
Vincent Lejeune 744efa4dca R600: Use shared op optimization when checking cycle compatibility
llvm-svn: 189981
2013-09-04 19:53:54 +00:00
Vincent Lejeune 7e2c83256b R600: Non vector only instruction can be scheduled on trans unit
llvm-svn: 189980
2013-09-04 19:53:46 +00:00
Vincent Lejeune 4d5c5e53d0 R600: Use SchedModel enum for is{Trans,Vector}Only functions
llvm-svn: 189979
2013-09-04 19:53:30 +00:00
Jim Grosbach 13654dd303 ARM: Teach A15 SDOptimizer to properly handle D-reg by-lane.
These instructions, such as vmul.f32, require the second source operand to
be in D0-D15 rather than the full D0-D31. When optimizing, make sure to
account for that by constraining the register class of a replacement virtual
register to be compatible with the virtual register(s) it's replacing.

I've been unsuccessful in creating a non-fragile regression test. This issue
was detected by the LLVM nightly test suite running on an A15 (Bullet).

PR17093: http://llvm.org/bugs/show_bug.cgi?id=17093
llvm-svn: 189972
2013-09-04 19:08:44 +00:00
Arnold Schwaighofer d7e8d92606 Swift: Only build vldm/vstm with q register aligned register lists
Unaligned vldm/vstm need more uops and therefore are slower in general on swift.

radar://14522102

llvm-svn: 189961
2013-09-04 17:41:16 +00:00
Silviu Baranga 5cba070ce2 Fix scheduling for vldm/vstm instructions that load/store more than 32 bytes on Cortex-A9. This also makes the existing code more compact.
llvm-svn: 189958
2013-09-04 17:05:18 +00:00
Venkatraman Govindaraju b803cec00e [Sparc] Fix an assertion failure while lowering fcmp on long double.
This assertion is triggered because an integer constant is created with wrong
  type.

llvm-svn: 189948
2013-09-04 15:15:20 +00:00
Hao Liu d4aede098f Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions:
sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshrun,sqshrn,uqshr,sqrshrn,uqrshrn,sshll,ushll
 and 4 convert instructions:
      scvtf,ucvtf,fcvtzs,fcvtzu

llvm-svn: 189925
2013-09-04 09:28:24 +00:00
Michael Gottesman c9f5859f81 Add llvm namespace to llvm::next.
llvm-svn: 189912
2013-09-04 04:26:09 +00:00
Michael Gottesman 114ac1a230 Use llvm::next() instead of incrementing begin iterators of std::vector.
Iterator of std::vector may be implemented as a raw pointer. In
this case begin iterators are rvalues and cannot be incremented.
For example, this is the case with STDCXX implementation of vector.

Patch by Konstantin Tokarev <annulen@yandex.ru>.

llvm-svn: 189911
2013-09-04 04:19:01 +00:00
Jim Grosbach 6c6b425b30 X86: Mark non-crashing report_fatal_errors() as such.
Previously, the clang crash handling code would kick in and give a crash
report for these, even though they're not that sort of error.

rdar://14882264

llvm-svn: 189878
2013-09-03 23:02:00 +00:00
Bill Wendling c656b8e402 WIP: Refactor some code so that it can be called by more than just one method. No functionality change.
llvm-svn: 189849
2013-09-03 20:59:07 +00:00
Jim Grosbach 20c925dbf2 Revert "Revert "ARM: Improve pattern for isel mul of vector by scalar.""
This reverts commit r189648.

Fixes for the previously failing clang-side arm_neon_intrinsics test
cases will be checked in separately.

llvm-svn: 189841
2013-09-03 20:08:17 +00:00
Richard Sandiford 113c870397 [SystemZ] Add support for TMHH, TMHL, TMLH and TMLL
For now this just handles simple comparisons of an ANDed value with zero.
The CC value provides enough information to do any comparison for a
2-bit mask, and some nonzero comparisons with more populated masks,
but that's all future work.

llvm-svn: 189819
2013-09-03 15:38:35 +00:00
Venkatraman Govindaraju 59039dc1bf [Sparc] Add support for soft long double (fp128).
llvm-svn: 189780
2013-09-03 04:11:59 +00:00
Craig Topper 8a1028f75e Add hadSideEffects=0 to some instructions.
llvm-svn: 189779
2013-09-03 03:56:17 +00:00
Venkatraman Govindaraju 01cb19f93c [Sparc] Implement spill and load for long double(f128) registers.
llvm-svn: 189768
2013-09-02 18:32:45 +00:00
Tilmann Scheller 63872ce19f ARM: Default to the Swift CPU when targeting armv7s/thumbv7s.
Test cases adjusted accordingly.

This fixes rdar://14871821.

llvm-svn: 189766
2013-09-02 17:09:01 +00:00
Tilmann Scheller 8f79ee99be Revert 189756 for now, it doesn't match what rdar://14871821 really wants.
What we really want is to enable Swift by default for *v7s triples (and there already seems to be some logic which attempts to do that). In that case the iOS version doesn't matter. 

llvm-svn: 189763
2013-09-02 15:48:17 +00:00
Tilmann Scheller f49c80178e ARM: Default to Swift when compiling for iOS 6 or later.
Test cases adjusted accordingly.

This fixes rdar://14871821.

llvm-svn: 189756
2013-09-02 12:01:58 +00:00
Craig Topper b25f0f5538 Create BEXTR instructions for (and ((sra or srl) x, imm), (2**size - 1)). Fixes PR17028.
llvm-svn: 189742
2013-09-02 07:53:17 +00:00
Elena Demikhovsky 402ee64f13 AVX-512: updated the list of high-latency instructions.
llvm-svn: 189740
2013-09-02 07:41:01 +00:00
Elena Demikhovsky 534015e550 AVX-512: gather-scatter tests; added foldable instructions;
Specify GATHER/SCATTER as heavy instructions.

llvm-svn: 189736
2013-09-02 07:12:29 +00:00
Elena Demikhovsky 4def4b088f AVX-512: Added GATHER and SCATTER instructions.
llvm-svn: 189729
2013-09-01 14:24:41 +00:00
Charles Davis 8bdfafd505 Move everything depending on Object/MachOFormat.h over to Support/MachO.h.
llvm-svn: 189728
2013-09-01 04:28:48 +00:00
Reed Kotler 5fdadcef7a Make sure we don't generate stubs for any of these functions because they
don't exist in libc. This is really not the right way to solve this problem;
but it's not clear to me at this time exactly what is the right way.
If we create stubs here, they will cause link errors because these functions
do not exist in libc.

llvm-svn: 189727
2013-09-01 04:12:59 +00:00
Benjamin Kramer bda73fff49 Mark an unreachable code path with llvm_unreachable. Pacifies GCC.
llvm-svn: 189726
2013-08-31 21:20:04 +00:00
Bill Schmidt eb8d6f7da0 [PowerPC] Fast-isel cleanup patch.
Here are a few miscellaneous things to tidy up the PPC64 fast-isel
implementation.  I corrected a couple of commentary lapses, and added
documentation of future opportunities.  I also implemented
TargetMaterializeAlloca, which I somehow forgot when I split up the
original huge patch.

Finally, I decided to delete SelectCmp.  I hadn't previously hooked it
in to TargetSelectInstruction(), and when I did I realized it wasn't
serving any useful purpose.  This is only useful for compares that
don't feed a branch in the same block, and to handle that we would
have to have logic to interpret i1 as a condition register.  This
could probably be done, but would require Unseemly Hackery, and
honestly does not seem worth the hassle.

This ends the current patch series.

llvm-svn: 189715
2013-08-31 02:33:40 +00:00
Bill Schmidt 9d9510d806 [PowerPC] Add integer truncation support to fast-isel.
This is the last substantive patch I'm planning for fast-isel in the
near future, adding fast selection of integer truncates.  There are
certainly more things that can be improved (many of which are called
out in FIXMEs), but for now we are catching most of the important
cases.

I'll document some of the remaining work in a cleanup patch shortly.

llvm-svn: 189706
2013-08-30 23:31:33 +00:00
Bill Schmidt 0954ea1b5e Correct partially defined variable
llvm-svn: 189705
2013-08-30 23:25:30 +00:00
Bill Schmidt 8470b0f96c [PowerPC] Call support for fast-isel.
This patch adds fast-isel support for calls (but not intrinsic calls
or varargs calls).  It also removes a badly-formed assert.  There are
some new tests just for calls, and also for folding loads into
arguments on calls to avoid extra extends.

llvm-svn: 189701
2013-08-30 22:18:55 +00:00
Richard Mitton 79917a913e Build fix
llvm-svn: 189699
2013-08-30 21:32:42 +00:00
Richard Mitton 576ee003d0 Fixed a bug where diassembling an instruction that had a prefix would cause LLVM to identify a 1-byte instruction, but then upon querying it for that 1-byte instruction would cause an undefined opcode.
llvm-svn: 189698
2013-08-30 21:19:48 +00:00
Reed Kotler c03807a3a5 Fix a problem with dual mips16/mips32 mode. When the underlying processor
has hard float, when you compile the mips32 code you have to make sure
that it knows to compile any mips32 routines as hard float. I need to clean
up the way mips16 hard float is specified but I need to first think through
all the details. Mips16 always has a form of soft float, the difference being
whether the underlying hardware has floating point. So it's not really
necessary to pass the -soft-float to llvm since soft-float is always true
for mips16 by virtue of the fact that it will not register floating point
registers. By using this fact, I can simplify the way this is all handled.

llvm-svn: 189690
2013-08-30 19:40:56 +00:00
Bill Schmidt 8d86fe7d6f [PowerPC] Add handling for conversions to fast-isel.
Yet another chunk of fast-isel code.  This one handles various
conversions involving floating-point.  (It also includes some
miscellaneous handling throughout the back end for LWA_32 and LWAX_32
that should have been part of the load-store patch.)

llvm-svn: 189677
2013-08-30 15:18:11 +00:00
Andrey Churbanov 3535e04483 Checking commit access; removed one space added in previous test checkin by Jim
llvm-svn: 189673
2013-08-30 14:40:24 +00:00
Benjamin Kramer 8f429384b5 X86: Add a description of the Intel Atom Silvermont CPU.
Currently this is just the atom model with SSE4.2 enabled.

llvm-svn: 189669
2013-08-30 14:05:32 +00:00
Craig Topper f78c19c3bb Fixup BZHI selection to remove an unneeded zero extension.
llvm-svn: 189656
2013-08-30 07:16:16 +00:00
Craig Topper 48a5d69ee1 Remove unused X86andn_flag node.
llvm-svn: 189654
2013-08-30 07:06:26 +00:00
Craig Topper 0bccad2d43 Teach X86 backend to create BMI2 BZHI instructions from (and X, (add (shl 1, Y), -1)). Fixes PR17038.
llvm-svn: 189653
2013-08-30 06:52:21 +00:00
Michael Gottesman b7ecc3e6af Revert "ARM: Improve pattern for isel mul of vector by scalar."
This reverts commit r189619.

The commit was breaking the arm_neon_intrinsic test.

llvm-svn: 189648
2013-08-30 05:36:14 +00:00
Andrew Trick 1a8313458f mi-sched: Precompute a PressureDiff for each instruction, adjust for liveness later.
Created SUPressureDiffs array to hold the per node PDiff computed during DAG building.

Added a getUpwardPressureDelta API that will soon replace the old
one. Compute PressureDelta here from the precomputed PressureDiffs.

Updating for liveness will come next.

llvm-svn: 189640
2013-08-30 03:49:48 +00:00
Bill Schmidt 057b04f662 [PowerPC] Handle selection of compare instructions in fast-isel.
Mostly trivial patch adding support for compares.  The meat of the
work was added with the branch support.

llvm-svn: 189639
2013-08-30 03:16:48 +00:00
Bill Schmidt 72e3d55a76 Remove bogus debug statement. Sheesh.
llvm-svn: 189638
2013-08-30 03:07:11 +00:00
Bill Schmidt ccecf26157 [PowerPC] Add loads, stores, and related things to fast-isel.
This is the next big chunk of fast-isel code.  The primary purpose is
to implement selection of loads and stores, but there is a lot of
drag-along to support this.  The common code to analyze addresses for
both loads and stores is substantial.  It's also necessary to add the
materialization code for global values.

Related to load-store processing is the code to fold loads into
integer extends, since otherwise we generate lots of redundant
instructions.  We also need to add some overrides to some FastEmit
routines to ensure we don't assign GPR 0 to a virtual register when
this would change the meaning of an instruction.

I added handling selection of a few binary arithmetic instructions, to
enable committing some test cases I wrote a while back.

Finally, ap couple of miscellaneous changes:
 * I cleaned up some poor style from a previous patch in
   PPCISelLowering.cpp, pointed out by David Blaikie.
 * I enlarged the Addr.Offset field to avoid sign problems with 32-bit
   offsets. 

llvm-svn: 189636
2013-08-30 02:29:45 +00:00
Jim Grosbach 04cc76dd53 ARM: Improve pattern for isel mul of vector by scalar.
In addition to recognizing when the multiply's second argument is
coming from an explicit VDUPLANE, also look for a plain scalar
f32 reference and reference it via the corresponding vector
lane.

rdar://14870054

llvm-svn: 189619
2013-08-29 22:41:46 +00:00
Cameron Esfahani 943908b78d Clean up some usage of Triple. The base class has methods for determining if the target is iOS and Linux.
llvm-svn: 189604
2013-08-29 20:23:14 +00:00
Elena Demikhovsky 980c6b08b1 AVX-512: added extend and truncate instructions.
llvm-svn: 189580
2013-08-29 11:56:53 +00:00
Hal Finkel b350ffd1b1 Add useAA() to TargetSubtargetInfo
There are several optional (off-by-default) features in CodeGen that can make
use of alias analysis. These features are important for generating code for
some kinds of cores (for example the (in-order) PPC A2 core). This adds a
useAA() function to TargetSubtargetInfo to allow these features to be enabled
by default on a per-subtarget basis.

Here is the first use of this function: To control the default of the
-enable-aa-sched-mi feature.

llvm-svn: 189563
2013-08-29 03:25:05 +00:00
Kevin Enderby 74946758a0 The darwin integrated assembler for X86 in 64-bit mode is not rejecting
32-bit absolute addressing in instructions likei this:

	mov $_f, %rsi

which is not supported in 64-bit mode.

rdar://8827134

llvm-svn: 189543
2013-08-29 00:19:03 +00:00
Joey Gouly daf0e378d2 [ARMv8]
Fix a few things in one swoop.

# Add some negative tests.
# Fix some formatting issues.
# Add some missing IsThumb / ARMv8
# Fix some outs / ins mistakes.

llvm-svn: 189490
2013-08-28 16:39:20 +00:00
Tim Northover f5769880d9 ARM: Use "dmb sy" for barriers on M-class CPUs
The usual default of "dmb ish" (inner-shareable) isn't even a valid instruction
on v6M or v7M (well, it does the same thing but software is strongly
discouraged from using it) so we should emit a full-system barrier there.

llvm-svn: 189483
2013-08-28 14:39:19 +00:00
Joey Gouly 179e2c0b14 [ARMv8] Add a missing IsThumb to t2LDAEXD.
llvm-svn: 189482
2013-08-28 14:33:35 +00:00