dc8bf9ec08
Thumb disassembler was erroneously rejecting "blx sp" instruction.
...
rdar://problem/9267838
llvm-svn: 129320
2011-04-11 23:33:30 +00:00
f922b20922
Change MRC and MRC2 instructions to model the output register properly
...
llvm-svn: 128085
2011-03-22 15:06:24 +00:00
90d1dfe4c6
Fix encoding and add parsing support for the arm/thumb CPS instruction:
...
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.
llvm-svn: 125489
2011-02-14 13:09:44 +00:00
d8f9b37f31
Add cdp/cdp2 instructions for thumb/thumb2
...
llvm-svn: 123929
2011-01-20 18:32:09 +00:00
cf99dc7eb9
Add mcr* and mr*c support to thumb targets
...
llvm-svn: 123917
2011-01-20 16:35:57 +00:00
2a0a3b43d7
Flag -> Glue, the ongoing saga
...
llvm-svn: 122513
2010-12-23 18:28:41 +00:00
cdcc4fc048
Fix a copy-pasto. When the tBR_JTr instruction was converted to using the
...
tPseudoInst class, its size was changed from "special" to "2 bytes". This is
incorrect because the jump table will no longer be taken into account when
calculating branch offsets.
<rdar://problem/8782216>
llvm-svn: 122303
2010-12-21 01:57:15 +00:00
b5743b9d76
Pseudo-ize the Thumb1 tBfar pattern. rdar://8777974
...
llvm-svn: 121990
2010-12-16 19:11:16 +00:00
f5b17c32d2
Add encodings for Thumb1 Spill and Restore pseudos.
...
llvm-svn: 121929
2010-12-16 00:38:41 +00:00
bfef309d11
Thumb1 had two patterns for the same load-from-constant-pool instruction.
...
Canonicalize on tLDRpci and remove tLDRcp.
llvm-svn: 121920
2010-12-15 23:52:36 +00:00
6217ecd634
Whitespace cleanups.
...
llvm-svn: 121914
2010-12-15 23:31:24 +00:00
1171e9e81d
Add some missing patterns now that tLDRB and tLDRH are split into reg and
...
immediate versions.
llvm-svn: 121819
2010-12-15 00:58:57 +00:00
5ab38b59e6
Comments and cleaning.
...
llvm-svn: 121809
2010-12-14 23:42:48 +00:00
509dc2a700
Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755
...
llvm-svn: 121798
2010-12-14 22:28:03 +00:00
ce4f87b3ba
Multiclassify the LDR/STR encoding patterns. The only functionality difference
...
is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.
llvm-svn: 121794
2010-12-14 22:10:49 +00:00
6dd0c07622
Use the integer scheduling intrinsic for integer loads and stores.
...
llvm-svn: 121765
2010-12-14 12:33:05 +00:00
092a7bdf9f
The tLDR et al instructions were emitting either a reg/reg or reg/imm
...
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.
The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.
There are some obvious cleanups here, which will happen shortly.
llvm-svn: 121747
2010-12-14 03:36:38 +00:00
b0fa127f60
Fix encoding of Thumb1 LDRB and STRB.
...
llvm-svn: 121581
2010-12-10 22:11:13 +00:00
e119da1146
Thumb unconditional branch binary encoding. rdar://8754994
...
llvm-svn: 121496
2010-12-10 18:21:33 +00:00
78485ad65e
Thumb conditional branch binary encodings. rdar://8745367
...
llvm-svn: 121493
2010-12-10 17:13:40 +00:00
0c4838bab7
Thumb ldr reg+imm offsets were encoded incorrectly. The scaling factor of the
...
t_addrmode_s# address modes is used for ASM printing, not for encoding.
<rdar://problem/8745375>
llvm-svn: 121417
2010-12-09 21:49:07 +00:00
62b68112da
Rename the encoder method for t_cbtarget to match.
...
llvm-svn: 121399
2010-12-09 19:04:53 +00:00
529c7e8d1f
Thumb needs a few different encoding schemes for branch targets. Rename
...
t_brtarget to be more specific.
llvm-svn: 121398
2010-12-09 19:01:46 +00:00
3392bfc8f3
The BLX instruction is encoded differently than the BL, because why not? In
...
particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0'
always. Going through the BL fixup encoding was trashing the "bit 0 is '0'"
invariant.
Attempt to get the encoding at slightly more correct with this.
llvm-svn: 121336
2010-12-09 00:39:08 +00:00
a7d6aa902a
Support the "target" encodings for the CB[N]Z instructions.
...
llvm-svn: 121308
2010-12-08 23:01:43 +00:00
8a6449c46e
Add support for loading from a constant pool.
...
llvm-svn: 121226
2010-12-08 01:57:09 +00:00
49bcd6ff85
Binary encoding for ARM tLDRspi and tSTRspi.
...
llvm-svn: 121186
2010-12-07 21:50:47 +00:00
327cf8ee5f
Refactor the ARM CMPz* patterns to just use the normal CMP instructions when
...
possible. They were duplicates for everything exception the source pattern
before.
llvm-svn: 121179
2010-12-07 20:41:06 +00:00
6e517d658e
Encode the literal field for tCMPzi instruction.
...
llvm-svn: 121153
2010-12-07 17:48:24 +00:00
9e1994698d
Add fixup for Thumb1 BL/BLX instructions.
...
llvm-svn: 121072
2010-12-06 23:57:07 +00:00
ce18d7ebb5
Encode condition code for Thumb1 conditional branch instruction.
...
llvm-svn: 120865
2010-12-04 00:20:40 +00:00
127d7485f1
Use correct variable names to match the patterns.
...
llvm-svn: 120857
2010-12-03 23:44:24 +00:00
a09cbbeef5
Match pattern operand names to expected encoding field names. This corrects the
...
operand encoding ordering of the instruction.
llvm-svn: 120852
2010-12-03 23:21:25 +00:00
e4fee20498
Remove incorrect BL target encoding (it's similar to, but not the same as the
...
ARM instruction). Add encoding of bits 13 and 11.
llvm-svn: 120849
2010-12-03 22:33:42 +00:00
f799579ddd
No need to declare EncoderMethod property anymore; just assign to it.
...
llvm-svn: 120831
2010-12-03 19:31:00 +00:00
6423c29e14
Add FIXMEs.
...
llvm-svn: 120824
2010-12-03 18:37:17 +00:00
36110d5d1a
Don't overwrite the opcode passed into the T1Special pattern.
...
llvm-svn: 120782
2010-12-03 02:02:58 +00:00
4d8ff86b9e
Add Thumb encoding for some more instructions.
...
llvm-svn: 120780
2010-12-03 01:55:47 +00:00
9c25894995
Formatting. It's all the rage!
...
llvm-svn: 120533
2010-12-01 02:36:55 +00:00
8ed14ae48a
More refactoring. This time the T1pI pattern.
...
llvm-svn: 120532
2010-12-01 02:28:08 +00:00
c25545a1a7
s/T1pIEncode/T1pILdStEncode/g
...
s/T1pIEncodeImm/T1pILdStEncodeImm/g
llvm-svn: 120524
2010-12-01 01:38:08 +00:00
7c646b924b
Renaming variables to coincide with documentation. No functionality change.
...
llvm-svn: 120522
2010-12-01 01:32:02 +00:00
490240a5d9
Refactor T1sI and T1sIt encodings into helper classes.
...
llvm-svn: 120518
2010-12-01 01:20:15 +00:00
4915f56669
Refactor the T1sIt encodings into a parent class to get rid of all of the "let"
...
statements.
llvm-svn: 120512
2010-12-01 00:48:44 +00:00
05632cb5cc
Rename operands to match ARM documentation. No functionality change.
...
llvm-svn: 120500
2010-11-30 23:54:45 +00:00
a9e3df7aa0
* Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same as
...
t_addrmode_s4, but with a different scaling factor.
* Encode the Thumb1 load and store instructions. This involved a bit of
refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and
were removed.
llvm-svn: 120482
2010-11-30 22:57:21 +00:00
811c936ed5
Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost
...
certainly be made more generic. But it does allow us to parse something like:
ldr r3, [r2, r4]
correctly in Thumb mode.
llvm-svn: 120408
2010-11-30 07:44:32 +00:00
ddce9f3757
Minor cleanups. No functional change.
...
llvm-svn: 120372
2010-11-30 00:50:22 +00:00
62718de2b9
Add correct encoding for "bl __aeabi_read_tp". However, the asm matcher isn't
...
able to match this yet.
llvm-svn: 120369
2010-11-30 00:34:08 +00:00
85a8a72d85
Add some encoding for the adr instruction. Labels still need to be finished.
...
llvm-svn: 120365
2010-11-30 00:18:30 +00:00
Johnny Chen