daed139420
Un-brain-dead-ify the lowering of part set for the reverse case.
...
llvm-svn: 37071
2007-05-15 02:26:52 +00:00
c7596efdad
Fix some subtle issues handling immediate values. This fixes
...
test/CodeGen/ARM/2007-05-14-InlineAsmCstCrash.ll
llvm-svn: 37069
2007-05-15 01:33:58 +00:00
4d728b0419
Added getNumExplicitOperands and findFirstPredOperand.
...
llvm-svn: 37064
2007-05-15 01:26:09 +00:00
e49c974a7c
implement a simple fneg optimization/propagation thing. This compiles:
...
CodeGen/PowerPC/fneg.ll into:
_t4:
fmul f0, f3, f4
fmadd f1, f1, f2, f0
blr
instead of:
_t4:
fneg f0, f3
fmul f0, f0, f4
fmsub f1, f1, f2, f0
blr
llvm-svn: 37054
2007-05-14 22:04:50 +00:00
e1595b6859
Only worry about intervening kill if there are more than one live ranges in the interval.
...
llvm-svn: 37052
2007-05-14 21:23:51 +00:00
c690cba7d9
Fix for PR1406:
...
v1 =
r2 = move v1
= op r2<kill>
...
r2 = move v1
= op r2<kill>
Clear the first r2 kill if v1 and r2 are joined.
llvm-svn: 37050
2007-05-14 21:10:05 +00:00
fc2377d4ed
When marking a register as being implicitly defined, make sure to clear its partial use info as well.
...
llvm-svn: 37046
2007-05-14 20:39:18 +00:00
764ae2a21b
Give names to the final result values of the part_set computations. This
...
just aids in readability and debugability of the output. No functional change.
llvm-svn: 37037
2007-05-14 17:21:17 +00:00
1ee0c8d563
Emit function debug frames in one atom. This will prevent us from generating incorrect assembler in case of both
...
debug information & exception information presented.
llvm-svn: 37019
2007-05-13 17:30:11 +00:00
bbaf55448b
Emit multiple common EH frames for multiple (including blank) personality
...
functions. This partly fixes PR1414: now we're restricted only to one
personality function per eh frame, not per module. Further work on
"multiple personalities" topic needs representative example.
llvm-svn: 37018
2007-05-13 15:42:26 +00:00
13da17843c
More DWARF-related things cleanup:
...
1. Fix PR1380
2. Apply Duncan's patch from PR1410
3. Insert workaround for "one personality function per module" as noted in PR1414
4. Emit correct debug frames for x86/linux. This partly fixes DebugInfo/2006-11-06-StackTrace.cpp: stack trace is
shown correctly, but arguments for function on top of stack are displayed incorrectly.
llvm-svn: 37015
2007-05-12 22:36:25 +00:00
bf283708f7
Get the size of auto arrays right, regardless of its changing size.
...
llvm-svn: 37006
2007-05-12 11:07:40 +00:00
79a71ec3ad
Fix http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070507/049516.html
...
llvm-svn: 36998
2007-05-11 23:14:43 +00:00
67286b1266
Perform correct actions numbers/sizes computation
...
llvm-svn: 36988
2007-05-11 08:47:35 +00:00
00d02442b0
Fix action No calculation in multiple-invoke-one-LP mode
...
llvm-svn: 36987
2007-05-11 08:23:57 +00:00
cc8f571bc8
Do not generate branches to entry block. This fixes several test suite
...
failures on PPC (can happen only when prologue code is null)
llvm-svn: 36979
2007-05-10 23:59:23 +00:00
ee02c7d2fb
Ooops. Some debugging stuff :)
...
llvm-svn: 36978
2007-05-10 22:38:46 +00:00
96142de3f0
Allow multiple invokes per landing pad. This (probably) fixes PR1410.
...
llvm-svn: 36977
2007-05-10 22:34:59 +00:00
b43fe52136
Later computations assume we are aligned at this point.
...
llvm-svn: 36975
2007-05-10 18:40:24 +00:00
ed5dad4306
TypeIds are indexed by j, not i
...
llvm-svn: 36974
2007-05-10 15:10:34 +00:00
6e16d09252
Make tail merging handle many more cases (all it can, I think).
...
llvm-svn: 36966
2007-05-10 01:01:49 +00:00
f325c2a65e
Can't fold the bit_convert is the store is a truncating store.
...
llvm-svn: 36962
2007-05-09 21:49:47 +00:00
192d09c2d9
Do not assert, when case range split metric is zero and JTs are not allowed: just emit binary tree in this case. This
...
fixes PR1403.
llvm-svn: 36959
2007-05-09 20:07:08 +00:00
31fd60ba0c
Change names from RA to something unique to get rid of naming conflicts with
...
certain linkers...
llvm-svn: 36944
2007-05-08 19:02:46 +00:00
9e17872c1d
Eliminate MarkVirtRegAliveInBlock recursion.
...
llvm-svn: 36943
2007-05-08 19:00:00 +00:00
562e45692e
Forgot a check.
...
llvm-svn: 36910
2007-05-07 21:36:06 +00:00
a4cf58a103
Enable a couple of xforms:
...
- (store (bitconvert v)) -> (store v) if resultant store does not require
higher alignment
- (bitconvert (load v)) -> (load (bitconvert*)v) if resultant load does not
require higher alignment
llvm-svn: 36908
2007-05-07 21:27:48 +00:00
9a25b3afcd
Handle some non-exit blocks in tail merging.
...
llvm-svn: 36907
2007-05-07 20:57:21 +00:00
671e8c4444
Parameter attributes on invoke calls were being lost due to the wrong
...
attribute index being used. Fix proposed by Anton Korobeynikov, who
asked me to implement and commit it for him. This is PR1398.
llvm-svn: 36906
2007-05-07 20:49:28 +00:00
a8fd7fdc25
Detabify
...
llvm-svn: 36891
2007-05-06 20:14:21 +00:00
e7da2d6ac3
Fix typo in comment.
...
llvm-svn: 36873
2007-05-06 13:37:16 +00:00
00282a21a5
Use the personality function that was registered with MMI rather than
...
hardwiring in the C++ one.
llvm-svn: 36789
2007-05-05 20:27:00 +00:00
07e6f3257c
Propagate alignment/volatility in two places.
...
Implement support for expanding a bitcast from an illegal vector type to
a legal one (e.g. 4xi32 -> 4xf32 in SSE1). This fixes PR1371 and
CodeGen/X86/2007-05-05-VecCastExpand.ll
llvm-svn: 36787
2007-05-05 19:39:05 +00:00
02528f5425
Spelling fix.
...
llvm-svn: 36781
2007-05-05 16:32:57 +00:00
4db0090339
Emit sections/directives in the proper order. This fixes PR1376. Also,
...
some small cleanup was made.
llvm-svn: 36780
2007-05-05 09:04:50 +00:00
4cb9eb81ef
A bitcast of a global variable may have been constant folded to a GEP -
...
handle this case too.
llvm-svn: 36745
2007-05-04 17:12:26 +00:00
044a0a8cfb
Don't create indexed load / store with zero offset!
...
llvm-svn: 36716
2007-05-03 23:52:19 +00:00
44a2ed66b1
Allow i/s to match (gv+c). This fixes CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll
...
and PR1382
llvm-svn: 36672
2007-05-03 16:54:34 +00:00
8c78a0bff0
Drop 'const'
...
llvm-svn: 36662
2007-05-03 01:11:54 +00:00
11940fbba3
Properly set arguments bitwidth of EHSELECT node
...
llvm-svn: 36654
2007-05-02 22:15:48 +00:00
e95c6ad802
Use 'static const char' instead of 'static const int'.
...
Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.
llvm-svn: 36652
2007-05-02 21:39:20 +00:00
41223586a2
Fix build error.
...
llvm-svn: 36648
2007-05-02 20:37:47 +00:00
b538f67b1a
Fix couple of bugs connected with eh info:
...
1. Correct output offsets on Linux
2. Fix "style" of personality function. It shouldn't be indirect.
llvm-svn: 36633
2007-05-01 22:23:12 +00:00
09f162ca6a
Do not use typeinfo to identify pass in pass manager.
...
llvm-svn: 36632
2007-05-01 21:15:47 +00:00
8cd28f0fb1
If call frame is not part of stack frame and no dynamic alloc, eliminateFrameIndex() must adjust SP offset with size of call frames.
...
llvm-svn: 36625
2007-05-01 09:01:42 +00:00
b68343cdd8
Forgot about chain result; also UNDEF cannot have multiple values.
...
llvm-svn: 36622
2007-05-01 08:53:39 +00:00
27a625a74b
llvm bug #1350 , parts 1, 2, and 3.
...
llvm-svn: 36618
2007-05-01 05:57:02 +00:00
77c545e6b8
Under normal circumstances, when a frame pointer is not required, we reserve
...
argument space for call sites in the function immediately on entry to the
current function. This eliminates the need for add/sub sp brackets around call
sites. However, this is not always a good idea. If the "call frame" is large and
the target load / store instructions have small immediate field to encode sp
offset, this can cause poor codegen. In the worst case, this can make it
impossible to scavenge a register if the reserved spill slot is pushed too far
apart from sp / fp.
llvm-svn: 36607
2007-05-01 00:52:08 +00:00
a684cd23a5
* Only turn a load to UNDEF if all of its outputs have no uses (indexed loads
...
produce two results.)
* Do not touch volatile loads.
llvm-svn: 36604
2007-05-01 00:38:21 +00:00
4dbbace4ff
Fix PR1228 and CodeGen/Generic/2007-04-30-LandingPadBranchFolding.ll
...
llvm-svn: 36602
2007-04-30 23:35:00 +00:00
f90c8fbd2b
print isLandingPad() for MBBs
...
llvm-svn: 36600
2007-04-30 23:12:53 +00:00
8cfd33b647
Continue refactoring inline asm code. If there is an earlyclobber output
...
register, preallocate all input registers and the early clobbered output.
This fixes PR1357 and CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
llvm-svn: 36599
2007-04-30 21:11:17 +00:00
6b77c3ed52
Updates.
...
llvm-svn: 36594
2007-04-30 18:42:09 +00:00
4333f8b1cf
refactor GetRegistersForValue to take OpInfo as an argument instead of various
...
pieces of it. No functionality change.
llvm-svn: 36592
2007-04-30 17:29:31 +00:00
ef07332504
refactor some code, no functionality change
...
llvm-svn: 36590
2007-04-30 17:16:27 +00:00
b58f93f273
Clean up multi-line asam string printing. Instead of printing:
...
# InlineAsm Start
subfc r3,r5,r4
subfze r4,r3
# InlineAsm End
print:
# InlineAsm Start
subfc r3,r5,r4
subfze r4,r3
# InlineAsm End
llvm-svn: 36589
2007-04-30 17:00:18 +00:00
412d61af43
generalize aggregate handling
...
llvm-svn: 36568
2007-04-29 18:58:03 +00:00
546ea7ea88
Implement review feedback
...
llvm-svn: 36564
2007-04-29 18:02:48 +00:00
401d8db381
memory operands that have a direct operand should have their stores created
...
before the copies into physregs are done. This avoids having flag operands
skip the store, causing cycles in the dag at sched time. This fixes infinite
loops on these tests:
test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll for PR1308
test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll
test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
test/CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll for PR828
llvm-svn: 36547
2007-04-28 21:12:06 +00:00
de339fa55d
eliminate more redundant constraint type analysis
...
llvm-svn: 36546
2007-04-28 21:03:16 +00:00
b2e55562ed
merge constraint type analysis stuff together.
...
llvm-svn: 36545
2007-04-28 21:01:43 +00:00
d7e3b6c442
Significant refactoring of the inline asm stuff, to support future changes.
...
No functionality change.
llvm-svn: 36544
2007-04-28 20:49:53 +00:00
b18f8f85e9
Implement review feedback. Aliasees can be either GlobalValue's or
...
bitcasts of them.
llvm-svn: 36537
2007-04-28 13:45:00 +00:00
1deacd61f4
memory inputs to an inline asm are required to have an address available.
...
If the operand is not already an indirect operand, spill it to a constant
pool entry or a stack slot.
This fixes PR1356 and CodeGen/X86/2007-04-27-InlineAsm-IntMemInput.ll
llvm-svn: 36536
2007-04-28 06:42:38 +00:00
d102ed0ac6
Fix CodeGen/Generic/2007-04-27-LargeMemObject.ll and
...
CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll
llvm-svn: 36534
2007-04-28 06:08:13 +00:00
4df3e8093b
Fix this to match change to InlineAsm class.
...
llvm-svn: 36524
2007-04-28 04:05:59 +00:00
1cbe208cda
Fix incorrect legalization of EHSELECTOR. This fixes
...
CodeGen/Generic/2007-04-14-EHSelectorCrash.ll and PR1326
llvm-svn: 36510
2007-04-27 17:12:52 +00:00
bf535fc8bd
Expand UINT_TO_FP in turns of SINT_TO_FP when UINTTOFP_* libcalls are not available.
...
llvm-svn: 36501
2007-04-27 07:33:31 +00:00
784fe9dbbb
improve EH global handling, patch by Duncan Sands.
...
llvm-svn: 36499
2007-04-27 01:20:11 +00:00
8131ab7c0f
enable Anton's shift/and switch lowering stuff! It now passes ppc bootstrap
...
successfully! woohoo...
llvm-svn: 36496
2007-04-26 21:09:43 +00:00
d7ae7f1659
Fixx off-by-one bug, which prevents llvm-gcc bootstrap on ppc32
...
llvm-svn: 36490
2007-04-26 20:44:04 +00:00
e131e3ac02
Fix a typo in a comment.
...
llvm-svn: 36485
2007-04-26 19:40:56 +00:00
910c80851e
Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion.
...
llvm-svn: 36483
2007-04-26 19:00:32 +00:00
ed23a1387e
Minor bug.
...
llvm-svn: 36473
2007-04-26 08:24:22 +00:00
43a17fe826
Be careful when to add implicit kill / dead operands. Don't add them during / post reg-allocation.
...
llvm-svn: 36458
2007-04-26 01:40:09 +00:00
0ba174534c
Match MachineFunction::UsedPhysRegs changes.
...
llvm-svn: 36452
2007-04-25 22:13:27 +00:00
d21968d11a
Change UsedPhysRegs from array bool to BitVector to save some space. Setting / getting its states now go through MachineFunction.
...
llvm-svn: 36451
2007-04-25 22:10:09 +00:00
d4549c5527
Clean up.
...
llvm-svn: 36449
2007-04-25 21:34:08 +00:00
0fbe14ab87
Data structure change to improve compile time (especially in debug mode).
...
llvm-svn: 36447
2007-04-25 19:34:00 +00:00
15f269afa3
This was lefted out. Fixed sumarray-dbl.
...
llvm-svn: 36445
2007-04-25 18:33:21 +00:00
a97b694c82
Implement aliases. This fixes PR1017 and it's dependent bugs. CFE part
...
will follow.
llvm-svn: 36435
2007-04-25 14:27:10 +00:00
7818c03c6b
Fix for PR1306.
...
- A register def / use now implicitly affects sub-register liveness but does
not affect liveness information of super-registers.
- Def of a larger register (if followed by a use later) is treated as
read/mod/write of a smaller register.
llvm-svn: 36434
2007-04-25 07:30:23 +00:00
11dc5abde1
Clean up.
...
llvm-svn: 36431
2007-04-25 07:18:20 +00:00
b975bebec1
support for >4G stack frames
...
llvm-svn: 36425
2007-04-25 04:30:24 +00:00
9bd98ea4c1
support > 4G stack objects
...
llvm-svn: 36422
2007-04-25 04:20:54 +00:00
cb0ed0cfbd
allow support for 64-bit stack objects
...
llvm-svn: 36420
2007-04-25 04:08:28 +00:00
01a26c74ae
Be more careful about folding op(x, undef) when we have vector operands.
...
This fixes CodeGen/X86/2007-04-24-VectorCrash.ll
llvm-svn: 36413
2007-04-25 00:00:45 +00:00
47917b697f
Assertion when using a 1-element vector for an add operation. Get the
...
real vector type in this case.
llvm-svn: 36402
2007-04-24 21:13:23 +00:00
4cfa616cee
Use '-1U' where '-1UL' is obvious overkill, eliminating gcc warnings about
...
tests always being true in the process.
llvm-svn: 36387
2007-04-24 01:24:20 +00:00
8653d29b45
modify per review commentary
...
llvm-svn: 36383
2007-04-23 23:33:31 +00:00
14a28f13c8
make EmitAlignment work the way Chris says it should
...
llvm-svn: 36368
2007-04-23 19:58:54 +00:00
8af6d5896f
PR400 phase 2. Propagate attributed load/store information through DAGs.
...
llvm-svn: 36356
2007-04-22 23:15:30 +00:00
4e91908f17
X86 TLS: Implement review feedback.
...
llvm-svn: 36318
2007-04-21 20:56:26 +00:00
0c1349e6bc
Revert Christopher Lamb's load/store alignment changes.
...
llvm-svn: 36309
2007-04-21 18:36:27 +00:00
bff50208c8
add support for alignment attributes on load/store instructions
...
llvm-svn: 36301
2007-04-21 08:16:25 +00:00
94314be0e0
Allow the lowering of ISD::GLOBAL_OFFSET_TABLE.
...
llvm-svn: 36290
2007-04-20 23:02:39 +00:00
2518889872
Implement "general dynamic", "initial exec" and "local exec" TLS models for
...
X86 32 bits.
llvm-svn: 36283
2007-04-20 21:38:10 +00:00
4c53d321aa
VarInfo::UsedBlocks is no longer used. Remove.
...
llvm-svn: 36250
2007-04-18 05:04:38 +00:00
f03c90bee6
allow SRL to simplify its operands, as it doesn't demand all bits as input.
...
llvm-svn: 36245
2007-04-18 03:06:49 +00:00
bf14f20632
When replacing a node in SimplifyDemandedBits, if the old node used any
...
single-use nodes, they will be dead soon. Make sure to remove them before
processing other nodes. This implements CodeGen/X86/shl_elim.ll
llvm-svn: 36244
2007-04-18 03:05:22 +00:00
15c1b820cc
fix a pasto
...
llvm-svn: 36242
2007-04-18 03:01:40 +00:00
b408e8f11d
Don't populate TryAgainList when coalescing only physical registers with virtual registers.
...
llvm-svn: 36240
2007-04-18 02:30:19 +00:00
a5a0c7c909
Increment use count of new virtuals created during PHI elimination.
...
llvm-svn: 36233
2007-04-18 00:36:11 +00:00
4aff52bf3d
Fix a bug in my previous patch, grabbing the shift amount width from the
...
wrong operand.
llvm-svn: 36223
2007-04-17 22:53:02 +00:00
9a861a8550
Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used.
...
This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }
into:
_baz:
srwi r2, r3, 1
extsh r3, r2
blr
on PPC, instead of:
_baz:
slwi r2, r3, 8
srwi r2, r2, 9
extsh r3, r2
blr
GCC produces:
_baz:
srwi r10,r4,24
insrwi r10,r3,24,0
srawi r9,r3,24
srawi r3,r10,9
extsh r3,r3
blr
This implements CodeGen/PowerPC/shl_elim.ll
llvm-svn: 36221
2007-04-17 21:14:16 +00:00
b881bdabd9
Copy coalescing change to prevent a physical register from being pin to a
...
long live interval that has low usage density.
1. Change order of coalescing to join physical registers with virtual
registers first before virtual register intervals become too long.
2. Check size and usage density to determine if it's worthwhile to join.
3. If joining is aborted, assign virtual register live interval allocation
preference field to the physical register.
4. Register allocator should try to allocate to the preferred register
first (if available) to create identify moves that can be eliminated.
llvm-svn: 36218
2007-04-17 20:32:26 +00:00
57b5214d59
Add a register allocation preference field; add a method to compute size of a live interval.
...
llvm-svn: 36216
2007-04-17 20:25:11 +00:00
8387cf1100
Keep track of number of uses within the function per virtual register.
...
llvm-svn: 36214
2007-04-17 20:22:11 +00:00
9ad5915559
SIGN_EXTEND_INREG does not demand its top bits. Give SimplifyDemandedBits
...
a chance to hack on it. This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }
into:
_baz:
slwi r2, r3, 8
srwi r2, r2, 9
extsh r3, r2
blr
instead of:
_baz:
srwi r2, r4, 24
rlwimi r2, r3, 8, 0, 23
srwi r2, r2, 9
extsh r3, r2
blr
This implements CodeGen/PowerPC/sign_ext_inreg1.ll
llvm-svn: 36212
2007-04-17 19:03:21 +00:00
58ec791b4c
Fix problems in the PartSet lowering having to do with incorrect bit width.
...
llvm-svn: 36180
2007-04-16 22:21:14 +00:00
fb80151c42
Removed tabs everywhere except autogenerated & external files. Add make
...
target for tabs checking.
llvm-svn: 36146
2007-04-16 18:10:23 +00:00
6bd7b7b30b
disable switch lowering using shift/and. It still breaks ppc bootstrap for
...
some reason. :( Will investigate.
llvm-svn: 36011
2007-04-14 19:39:41 +00:00
8a1a84f96e
Fix PR1325: Case range optimization was performed in the case it
...
shouldn't. Also fix some "latent" bug on 64-bit platforms
llvm-svn: 35990
2007-04-14 13:25:55 +00:00
7196f09edc
disable shift/and lowering to work around PR1325 for now.
...
llvm-svn: 35985
2007-04-14 02:26:56 +00:00
e288040abf
Fix PR1323 : we haven't updated phi nodes in good manner :)
...
llvm-svn: 35963
2007-04-13 06:53:51 +00:00
1b9213730f
Make sure intrinsics that are lowered to functions make the function weak
...
linkage so we only end up with one of them in a program. These are, after
all overloaded and templatish in nature.
llvm-svn: 35956
2007-04-12 21:53:38 +00:00
0f2f65f723
Fix bugs in generated code for part_select and part_set so that llc doesn't
...
barf when CBE is run with a program that contains these intrinsics.
llvm-svn: 35946
2007-04-12 13:30:14 +00:00
83faeb7611
Fix a bug in PartSet. The replacement value needs to be zext or trunc to
...
the size of the value, not just zext. Also, give better names to two BBs.
llvm-svn: 35945
2007-04-12 12:46:33 +00:00
5111499136
the result of an inline asm copy can be an arbitrary VT that the register
...
class supports. In the case of vectors, this means we often get the wrong
type (e.g. we get v4f32 instead of v8i16). Make sure to convert the vector
result to the right type. This fixes CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll
llvm-svn: 35944
2007-04-12 06:00:20 +00:00
a77cb3ce68
fold noop vbitconvert instructions
...
llvm-svn: 35943
2007-04-12 05:58:43 +00:00
784a68a702
Fix weirdness handling single element vectors.
...
llvm-svn: 35941
2007-04-12 04:44:28 +00:00
c6251a7dfd
For PR1284:
...
Implement the "part_set" intrinsic.
llvm-svn: 35938
2007-04-12 02:48:46 +00:00
18e4ac4107
fix an infinite loop compiling ldecod, notice by JeffC.
...
llvm-svn: 35910
2007-04-11 16:51:53 +00:00
a083ffcad7
Fix this harder.
...
llvm-svn: 35888
2007-04-11 06:50:51 +00:00
c5f85d3738
don't create shifts by zero, fix some problems with my previous patch
...
llvm-svn: 35887
2007-04-11 06:43:25 +00:00
65786b078c
Teach the codegen to turn [aez]ext (setcc) -> selectcc of 1/0, which often
...
allows other simplifications. For example, this compiles:
int isnegative(unsigned int X) {
return !(X < 2147483648U);
}
Into this code:
x86:
movl 4(%esp), %eax
shrl $31, %eax
ret
arm:
mov r0, r0, lsr #31
bx lr
thumb:
lsr r0, r0, #31
bx lr
instead of:
x86:
cmpl $0, 4(%esp)
sets %al
movzbl %al, %eax
ret
arm:
mov r3, #0
cmp r0, #0
movlt r3, #1
mov r0, r3
bx lr
thumb:
mov r2, #1
mov r1, #0
cmp r0, #0
blt LBB1_2 @entry
LBB1_1: @entry
cpy r2, r1
LBB1_2: @entry
cpy r0, r2
bx lr
Testcase here: test/CodeGen/Generic/ispositive.ll
llvm-svn: 35883
2007-04-11 05:32:27 +00:00
41189c63cc
Codegen integer abs more efficiently using the trick from the PPC CWG. This
...
improves codegen on many architectures. Tests committed as CodeGen/*/iabs.ll
X86 Old: X86 New:
_test: _test:
movl 4(%esp), %ecx movl 4(%esp), %eax
movl %ecx, %eax movl %eax, %ecx
negl %eax sarl $31, %ecx
testl %ecx, %ecx addl %ecx, %eax
cmovns %ecx, %eax xorl %ecx, %eax
ret ret
PPC Old: PPC New:
_test: _test:
cmpwi cr0, r3, -1 srawi r2, r3, 31
neg r2, r3 add r3, r3, r2
bgt cr0, LBB1_2 ; xor r3, r3, r2
LBB1_1: ; blr
mr r3, r2
LBB1_2: ;
blr
ARM Old: ARM New:
_test: _test:
rsb r3, r0, #0 add r3, r0, r0, asr #31
cmp r0, #0 eor r0, r3, r0, asr #31
movge r3, r0 bx lr
mov r0, r3
bx lr
Thumb Old: Thumb New:
_test: _test:
neg r2, r0 asr r2, r0, #31
cmp r0, #0 add r0, r0, r2
bge LBB1_2 eor r0, r2
LBB1_1: @ bx lr
cpy r0, r2
LBB1_2: @
bx lr
Sparc Old: Sparc New:
test: test:
save -96, %o6, %o6 save -96, %o6, %o6
sethi 0, %l0 sra %i0, 31, %l0
sub %l0, %i0, %l0 add %i0, %l0, %l1
subcc %i0, -1, %l1 xor %l1, %l0, %i0
bg .BB1_2 restore %g0, %g0, %g0
nop retl
.BB1_1: nop
or %g0, %l0, %i0
.BB1_2:
restore %g0, %g0, %g0
retl
nop
It also helps alpha/ia64 :)
llvm-svn: 35881
2007-04-11 05:11:38 +00:00
a472f66dd0
For PR1146:
...
Put the parameter attributes in their own ParamAttr name space. Adjust the
rest of llvm as a result.
llvm-svn: 35877
2007-04-11 02:44:20 +00:00
f269d84ca0
apparently some people commit without building the tree, or they forget to
...
commit a LOT of files.
llvm-svn: 35858
2007-04-10 03:20:39 +00:00
e0bbbd3774
No longer needed.
...
llvm-svn: 35850
2007-04-09 23:42:32 +00:00
35f0417ec1
remove dead target hooks.
...
llvm-svn: 35847
2007-04-09 23:34:08 +00:00
39f65335d5
remove some dead target hooks, subsumed by isLegalAddressingMode
...
llvm-svn: 35840
2007-04-09 22:27:04 +00:00
da964a2852
Use integer log for metric calculation
...
llvm-svn: 35834
2007-04-09 21:57:03 +00:00
0475f3b4e9
Unbreak VC++ build.
...
llvm-svn: 35817
2007-04-09 14:32:59 +00:00
506eaf7915
Next stage into switch lowering refactoring
...
1. Fix some bugs in the jump table lowering threshold
2. Implement much better metric for optimal pivot selection
3. Tune thresholds for different lowering methods
4. Implement shift-and trick for lowering small (<machine word
length) cases with few destinations. Good testcase will follow.
llvm-svn: 35816
2007-04-09 12:31:58 +00:00
71b79e3d99
For PR1146:
...
Adapt handling of parameter attributes to use the new ParamAttrsList class.
llvm-svn: 35814
2007-04-09 06:17:21 +00:00
7b2decfa0a
implement CodeGen/X86/inline-asm-x-scalar.ll:test3
...
llvm-svn: 35802
2007-04-09 05:31:20 +00:00
18d6718e78
add some assertions
...
llvm-svn: 35800
2007-04-09 05:23:13 +00:00
f73d215023
Fix a bug introduced with my previous patch, where it didn't correctly handle
...
instructions which replace themselves when FI's are rewritten (common on ppc).
This fixes CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll
llvm-svn: 35789
2007-04-09 01:19:33 +00:00
0df5357436
Fix CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll and PR1308:
...
some instructions can have multiple frame indices in them. If this happens,
rewrite all of them.
llvm-svn: 35785
2007-04-09 00:46:10 +00:00
b49917da92
Fix PR1316
...
llvm-svn: 35783
2007-04-09 00:33:58 +00:00
e55ecfb870
Fix for CodeGen/X86/2007-04-08-InlineAsmCrash.ll and PR1314
...
llvm-svn: 35779
2007-04-08 22:23:26 +00:00
1c741e95d3
minor comment fix
...
llvm-svn: 35696
2007-04-06 17:47:14 +00:00
85460acfbf
Change the bit_part_select (non)implementation from "return 0" to abort.
...
llvm-svn: 35679
2007-04-05 01:20:18 +00:00
cce90f55ed
Implement the llvm.bit.part_select.iN.iN.iN overloaded intrinsic.
...
llvm-svn: 35678
2007-04-04 23:48:25 +00:00
915e61736b
Properly emit range comparisons for switch cases, where neighbour cases
...
go to the same destination. Now we're producing really good code for
switch-lower-feature.ll testcase
llvm-svn: 35672
2007-04-04 21:14:49 +00:00
8be98c1572
Re-materialize all loads from fixed stack slots.
...
llvm-svn: 35660
2007-04-04 07:40:01 +00:00
2bf2aadd9a
Trivially re-materializable instructions have spill weights that are half of what it would be otherwise.
...
llvm-svn: 35658
2007-04-04 07:04:55 +00:00
06a7041ff9
Bad bad bug. findRegisterUseOperand() returns -1 if a use if not found.
...
llvm-svn: 35618
2007-04-03 06:43:29 +00:00
16627a542f
1. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL.
...
2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL
patterns. This was motivated by the X86/rotate.ll testcase, which should now
generate code for other platforms (and soon-to-come platforms.) Rewrote code
slightly to make it easier to read.
llvm-svn: 35605
2007-04-02 21:36:32 +00:00
476fb6a5c9
Ugh. Copy coalescer does not update register numbers.
...
llvm-svn: 35600
2007-04-02 18:49:18 +00:00
fad9bd6b92
For PR1297:
...
Make sure that the CTPOP result is casted to i32 as the bit counting
intrinsics all return i32 now (this affects CTLZ and CTTZ as well).
llvm-svn: 35567
2007-04-02 01:01:49 +00:00
6bba6c8143
For PR1297:
...
Support overloaded intrinsics bswap, ctpop, cttz, ctlz.
llvm-svn: 35547
2007-04-01 07:35:23 +00:00
3a0843e734
For PR1297:
...
Adjust for changes in the bit counting intrinsics. They all return i32
now so we have to trunc/zext the DAG node accordingly.
llvm-svn: 35546
2007-04-01 07:34:11 +00:00
a090ffb2ab
For PR1297:
...
Change getOperationName to return std::string instead of const char*
llvm-svn: 35545
2007-04-01 07:32:19 +00:00
f6a6d3c8b0
move a bunch of code out of the sdisel pass into its own opt pass "codegenprepare".
...
llvm-svn: 35529
2007-03-31 04:18:03 +00:00
f2d71d49e2
switch TL::getValueType to use MVT::getValueType.
...
llvm-svn: 35527
2007-03-31 04:05:24 +00:00
bafc837c83
Add a -print-lsr-output option to LLC, to print the output of the LSR pass.
...
llvm-svn: 35522
2007-03-31 00:24:43 +00:00
ac3f81508c
add one addressing mode description hook to rule them all.
...
llvm-svn: 35520
2007-03-30 23:14:50 +00:00
4bbd2eefba
Fix incorrect combination of different loads. Reenable zext-over-truncate
...
combination.
llvm-svn: 35517
2007-03-30 21:38:07 +00:00
9a2a7b174a
Don't add the same MI to register reuse "last def/use" twice if it reads the
...
register more than once.
llvm-svn: 35513
2007-03-30 20:21:35 +00:00
48dd5e7d44
Bug fix for PR1279. When isDead is propagate by copy coalescing, we keep length
...
of dead def live interval at 1 to avoid multiple def's targeting the same
register. The previous patch missed a case where the source operand is live-in.
In that case, remove the whole interval.
llvm-svn: 35512
2007-03-30 20:18:35 +00:00
ccee35fd0d
Disable load width reduction xform of variant (zext (truncate load x)) for
...
big endian targets until llvm-gcc build issue has been resolved.
llvm-svn: 35449
2007-03-29 07:56:46 +00:00
86de3a009d
New entries.
...
llvm-svn: 35445
2007-03-29 02:48:56 +00:00
d771485d89
Notes on re-materialization.
...
llvm-svn: 35420
2007-03-28 08:30:04 +00:00
603e49c6da
Move rematerialization out of beta.
...
llvm-svn: 35419
2007-03-28 08:26:40 +00:00
4388043b25
Scale 1 is always ok.
...
llvm-svn: 35407
2007-03-28 01:55:52 +00:00
c2cba18f2b
Remove isLegalAddressImmediate.
...
llvm-svn: 35406
2007-03-28 01:53:55 +00:00
07c42d43a2
GEP index sinking fixes:
...
1) Take address scale into consideration. e.g. i32* -> scale 4.
2) Examine all the users of GEP.
3) Generalize to inter-block GEP's (no longer uses loopinfo).
4) Don't do xform if GEP has other variable index(es).
llvm-svn: 35403
2007-03-28 01:49:39 +00:00
b41697c006
Fix for PR1279. Dead def has a live interval of length 1. Copy coalescing should
...
not violate that.
llvm-svn: 35396
2007-03-28 01:30:37 +00:00
37a0bfe128
Remove dead code
...
llvm-svn: 35380
2007-03-27 12:05:48 +00:00
3a9d68181a
Split big monster into small helpers. No functionality change.
...
llvm-svn: 35379
2007-03-27 11:29:11 +00:00
c42406b5ad
SDISel does not preserve all, it changes CFG and other info.
...
llvm-svn: 35376
2007-03-27 00:53:36 +00:00
fdbdf43632
Don't call getOperandConstraint() if operand index is greater than
...
TID->numOperands.
llvm-svn: 35375
2007-03-27 00:48:28 +00:00
4a09b1b5be
Fix for PR1266. Don't mark a two address operand IsKill.
...
llvm-svn: 35365
2007-03-26 22:40:42 +00:00
ec3ac316e2
Change findRegisterUseOperand() to return operand index instead.
...
llvm-svn: 35363
2007-03-26 22:37:45 +00:00
fd18a0cdf4
Fix reversed logic in getRegsUsed. Rename RegStates to RegsAvailable to
...
hopefully forestall similar errors.
llvm-svn: 35362
2007-03-26 22:23:54 +00:00
8275f0e0af
SIGN_EXTEND_INREG requires one extra operand, a ValueType node.
...
llvm-svn: 35350
2007-03-26 07:12:51 +00:00
7037826c86
First step of switch lowering refactoring: perform worklist-driven
...
strategy, emit JT's where possible.
llvm-svn: 35338
2007-03-25 15:07:15 +00:00
77f0479833
Implement support for vector operands to inline asm, implementing
...
CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll
llvm-svn: 35332
2007-03-25 05:00:54 +00:00
3d7efa2586
implement initial support for the silly X constraint. Testcase here: CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll
...
llvm-svn: 35327
2007-03-25 04:35:41 +00:00
843e44503c
Implement CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll
...
llvm-svn: 35324
2007-03-25 02:18:14 +00:00
d685514e2e
switch TargetLowering::getConstraintType to take the entire constraint,
...
not just the first letter. No functionality change.
llvm-svn: 35322
2007-03-25 02:14:49 +00:00
2a991268f7
don't rely on ADL
...
llvm-svn: 35299
2007-03-24 17:37:03 +00:00
b7051f596a
Adjust offset to compensate for big endian machines.
...
llvm-svn: 35293
2007-03-24 00:02:43 +00:00
a883b58caf
Make sure SEXTLOAD of the specific type is supported on the target.
...
llvm-svn: 35289
2007-03-23 22:13:36 +00:00
e2f5f24e8e
Also replace uses of SRL if that's also folded during ReduceLoadWidth().
...
llvm-svn: 35286
2007-03-23 20:55:21 +00:00
a824e79f06
A couple of bug fixes for reducing load width xform:
...
1. Address offset is in bytes.
2. Make sure truncate node uses are replaced with new load.
llvm-svn: 35274
2007-03-23 02:16:52 +00:00
dcb291faa4
Change uses of Function::front to Function::getEntryBlock for readability.
...
llvm-svn: 35265
2007-03-22 16:38:57 +00:00
464dc9b74c
More opportunities to reduce load size.
...
llvm-svn: 35254
2007-03-22 01:54:19 +00:00
a20815e157
Fix for PR1257. Bug in live range shortening as a result of copy coalescing
...
where the destination is dead.
llvm-svn: 35252
2007-03-22 01:26:05 +00:00
0c6bb5eab7
repair x86 performance, dejagnu problems from previous change
...
llvm-svn: 35245
2007-03-21 21:51:52 +00:00
d63baead9b
fold (truncate (srl (load x), c)) -> (smaller load (x+c/vt bits))
...
llvm-svn: 35239
2007-03-21 20:14:05 +00:00
3578dd61c6
Potential spiller improvement.
...
llvm-svn: 35228
2007-03-20 22:22:38 +00:00
bacf4acf65
do not share old induction variables when this would result in invalid
...
instructions (that would have to be split later)
llvm-svn: 35227
2007-03-20 21:54:54 +00:00
d05a1a2ade
maintain LiveIn when splitting blocks (register scavenging needs it)
...
llvm-svn: 35226
2007-03-20 21:35:06 +00:00
1baf5c84ab
Fix some VC++ warnings.
...
llvm-svn: 35224
2007-03-20 20:43:18 +00:00
971aa18867
Code clean up.
...
llvm-svn: 35220
2007-03-20 20:09:03 +00:00
550cf0369c
Minor bug.
...
llvm-svn: 35219
2007-03-20 19:32:11 +00:00
25878b45f5
CopyToReg source operand can be a physical register.
...
llvm-svn: 35213
2007-03-20 16:46:44 +00:00
0e3278e505
First cut trivial re-materialization support.
...
llvm-svn: 35208
2007-03-20 08:13:50 +00:00
25d00d545d
Remove -reduce-joining-phys-regs options. Make it on by default.
...
llvm-svn: 35165
2007-03-19 18:08:26 +00:00
c5e74f6404
Minor bug fix.
...
llvm-svn: 35153
2007-03-19 04:22:35 +00:00
d8f2e4fe4c
- Merge UsedBlocks info after two virtual registers are coalesced.
...
- Use distance to closest use to determine whether to abort coalescing.
llvm-svn: 35141
2007-03-18 09:05:55 +00:00
5382426577
Keep UsedBlocks info accurate.
...
llvm-svn: 35140
2007-03-18 09:02:31 +00:00
f6f043332f
Track the BB's where each virtual register is used.
...
llvm-svn: 35135
2007-03-17 09:29:54 +00:00
7b2a001669
Joining a live interval of a physical register with a virtual one can turn out
...
to be really bad. Once they are joined they are not broken apart. Also, physical
intervals cannot be spilled!
Added a heuristic as a workaround for this. Be careful coalescing with a
physical register if the virtual register uses are "far". Check if there are
uses in the same loop as the source (copy instruction). Check if it is in the
loop preheader, etc.
llvm-svn: 35134
2007-03-17 09:27:35 +00:00
a2465dfc07
Use SmallSet instead of std::set.
...
llvm-svn: 35133
2007-03-17 08:53:30 +00:00
be22235790
If sdisel has decided to sink GEP index expression into any BB. Replace all uses
...
in that BB.
llvm-svn: 35132
2007-03-17 08:22:49 +00:00
c5bc763f50
Turn on GEP index sinking by default.
...
llvm-svn: 35127
2007-03-16 18:32:30 +00:00
0a9d0cabaf
Stupid bug.
...
llvm-svn: 35126
2007-03-16 17:50:20 +00:00
009ea54262
Sink a binary expression into its use blocks if it is a loop invariant
...
computation used as GEP indexes and if the expression can be folded into
target addressing mode of GEP load / store use types.
llvm-svn: 35123
2007-03-16 08:46:27 +00:00
a2a2fd1e55
Added isLegalAddressExpression hook to test if the given expression can be
...
folded into target addressing mode for the given type.
llvm-svn: 35121
2007-03-16 08:42:32 +00:00
88de94a4fb
Debugging output stuff.
...
llvm-svn: 35117
2007-03-15 21:19:28 +00:00
b9e3db67fb
Estimate a cost using the possible number of scratch registers required and use
...
it as a late BURR scheduling tie-breaker.
Intuitively, it's good to push down instructions whose results are liveout so
their long live ranges won't conflict with other values which are needed inside
the BB. Further prioritize liveout instructions by the number of operands which
are calculated within the BB.
llvm-svn: 35109
2007-03-14 22:43:40 +00:00
2874855302
Try schedule def + use closer whne Sethi-Ullman numbers are the same.
...
e.g.
t1 = op t2, c1
t3 = op t4, c2
and the following instructions are both ready.
t2 = op c3
t4 = op c4
Then schedule t2 = op first.
i.e.
t4 = op c4
t2 = op c3
t1 = op t2, c1
t3 = op t4, c2
This creates more short live intervals which work better with the register
allocator.
llvm-svn: 35089
2007-03-13 23:25:11 +00:00
b7004fd889
More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale.
...
llvm-svn: 35076
2007-03-12 23:37:10 +00:00
df7949a8d0
If a virtual register is already marked alive in this block, that means it is
...
alive in one of the successor block. Do not add it to the kill list.
llvm-svn: 35041
2007-03-09 09:48:56 +00:00
9bc8d4b6f2
Print preds / succs BB numbers.
...
llvm-svn: 35040
2007-03-09 08:29:08 +00:00
91b0790297
Avoid variable shadowing.
...
llvm-svn: 35039
2007-03-09 06:02:17 +00:00
ce8aba03ee
implement support for floating point constants used as inline asm memory operands.
...
llvm-svn: 35033
2007-03-08 22:29:47 +00:00
b7bc3f2d30
make this fail even in non-assert builds.
...
llvm-svn: 35025
2007-03-08 07:07:03 +00:00
ed4b303c10
Refactoring of formal parameter flags. Enable properly use of
...
zext/sext/aext stuff.
llvm-svn: 35008
2007-03-07 16:25:09 +00:00
dd6ce6900e
Cleanup: make SetCounter an instance variable
...
llvm-svn: 35007
2007-03-07 08:25:02 +00:00
8a1d09d079
Avoid combining indexed load further.
...
llvm-svn: 35005
2007-03-07 08:07:03 +00:00
942fda027f
Fix DWARF debugging information on x86/Linux and (hopefully)
...
Mingw32/Cygwin targets. This fixes PR978
llvm-svn: 35000
2007-03-07 02:47:57 +00:00
24f65cc91e
Minor bug fix.
...
llvm-svn: 34985
2007-03-06 21:58:15 +00:00
b0743b5d6a
Now LoopStrengthReduce is a LoopPass.
...
llvm-svn: 34984
2007-03-06 21:14:09 +00:00
13780ac7db
big endian 32-bit systems (e.g. ppc32) want to return the high reg first, not
...
the lo-reg first. This is fallout from my ppc calling conv change yesterday,
it fixes test/ExecutionEngine/2003-05-06-LivenessClobber.llx
llvm-svn: 34983
2007-03-06 20:01:06 +00:00
6c5e0ad71c
Small eye-candy: use asciz directive everywhere, where possible.
...
llvm-svn: 34981
2007-03-06 19:25:02 +00:00
c1b21857a4
If target decides to create an emergency spill slot, make sure it's closest to SP or frame pointer.
...
llvm-svn: 34965
2007-03-06 10:02:38 +00:00
372c2c69f8
Register scavenger is now capable of scavenging. It spills a register whose use of furthest away to make it available.
...
llvm-svn: 34964
2007-03-06 10:01:25 +00:00
f0b9316552
Enumerate SDISel formal parameter attributes. Make use of new
...
enumeration.
llvm-svn: 34960
2007-03-06 06:10:33 +00:00
b622c11f77
Unbreak VC++ build.
...
llvm-svn: 34917
2007-03-05 00:00:42 +00:00
47206667c0
fold away addc nodes when we know there cannot be a carry-out.
...
llvm-svn: 34913
2007-03-04 20:40:38 +00:00
2dcc6e7f58
generalize
...
llvm-svn: 34910
2007-03-04 20:08:45 +00:00
e2e13caeb2
canonicalize constants to the RHS of addc/adde. If nothing uses the carry out of
...
addc, turn it into add.
This allows us to compile:
long long test(long long A, unsigned B) {
return (A + ((long long)B << 32)) & 123;
}
into:
_test:
movl $123, %eax
andl 4(%esp), %eax
xorl %edx, %edx
ret
instead of:
_test:
xorl %edx, %edx
movl %edx, %eax
addl 4(%esp), %eax ;; add of zero
andl $123, %eax
ret
llvm-svn: 34909
2007-03-04 20:03:15 +00:00
362621c7ae
eliminate some ops if they have an undef RHS
...
llvm-svn: 34908
2007-03-04 20:01:46 +00:00
b8825b8c04
Remove unneeded header file.
...
llvm-svn: 34903
2007-03-04 04:41:04 +00:00
ca401aac31
Fix CodeGen/Generic/fpowi-promote.ll and PR1239
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llvm-svn: 34893
2007-03-03 23:43:21 +00:00
567b9254cd
Add an expand action for ISD label which just deletes the label.
...
This "fixes" PR1238.
llvm-svn: 34890
2007-03-03 19:21:38 +00:00
d74cb0e194
Only propagate IsKill if the last use is a kill.
...
llvm-svn: 34878
2007-03-03 06:32:37 +00:00
323cf8f602
http://llvm.org/bugs/show_bug.cgi?id=1237
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llvm-svn: 34875
2007-03-03 06:18:18 +00:00
3fd728596e
Watch out for cases like this:
...
entry (0x8b056f0, LLVM BB @0x8b01b30, ID#0):
Live Ins: %r0 %r1 %r2 %r3
%reg1032 = tMOVrr %r3<kill>
%reg1033 = tMOVri8 1
%reg1034 = tMOVri8 0
tCMPi8 %reg1029<kill>, 0
tBcc mbb<entry,0x8b06a10>, 0
Successors according to CFG: 0x8b06980 0x8b06a10
entry (0x8b06980, LLVM BB @0x8b01b30, ID#12):
Predecessors according to CFG: 0x8b056f0
%reg1036 = tMOVrr %reg1034<kill>
Successors according to CFG: 0x8b06a10
entry (0x8b06a10, LLVM BB @0x8b01b30, ID#13):
Predecessors according to CFG: 0x8b056f0 0x8b06980
%reg1024<dead> = tMOVrr %reg1030<kill>
...
reg1030 and r1 have already been joined. When reg1024 and reg1030 are joined,
r1 live range from function entry to the tMOVrr instruction are dead. Eliminate
r1 from the livein set of the entry BB, not the BB where the copy is.
llvm-svn: 34866
2007-03-03 02:18:00 +00:00
155ede21e0
Mark dead def as unused.
...
llvm-svn: 34844
2007-03-02 10:43:16 +00:00
9d615d1e70
Dead live-in detection bug.
...
llvm-svn: 34843
2007-03-02 10:41:15 +00:00
6605c5dbee
- Keep track all def and uses of stack slot available in register.
...
- Available value use may be deleted (e.g. noop move).
llvm-svn: 34841
2007-03-02 08:52:00 +00:00
08f2f0d145
Invalidate last use of a reused register if the use is a deleted noop copy.
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llvm-svn: 34839
2007-03-02 05:41:42 +00:00
82af5943d1
Emit eh filter info.
...
llvm-svn: 34805
2007-03-01 20:26:43 +00:00
6458e6acb9
Collect eh filter info.
...
llvm-svn: 34804
2007-03-01 20:25:32 +00:00
Reid Spencer