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2386 Commits

Author SHA1 Message Date
Dan Gohman 057240f4f0 Fold adds and subtracts of zero immediately, instead of waiting 
for dagcombine to do this.

llvm-svn: 51886
 2008-06-02 22:27:05 +00:00
Scott Michel d831cc49e5 Add necessary 64-bit support so that gcc frontend compiles (mostly). Current 
issue is operand promotion for setcc/select... but looks like the fundamental
stuff is implemented for CellSPU.

llvm-svn: 51884
 2008-06-02 22:18:03 +00:00
Dan Gohman 9a19f33842 Remove an unused variable. 
llvm-svn: 51807
 2008-05-31 01:44:25 +00:00
Dan Gohman 8807147ada Remove an unused variable. 
llvm-svn: 51721
 2008-05-30 00:56:36 +00:00
Dan Gohman 714663ab94 Expand small memmovs using inline code. Set the X86 threshold for expanding 
memmove to a more plausible value, now that it's actually being used.

llvm-svn: 51696
 2008-05-29 19:42:22 +00:00
Evan Cheng 5e28227dbd Implement vector shift up / down and insert zero with ps{rl}lq / ps{rl}ldq. 
llvm-svn: 51667
 2008-05-29 08:22:04 +00:00
Duncan Sands 698348dfac Fix some constructs that gcc-4.4 warns about. 
llvm-svn: 51591
 2008-05-27 11:50:51 +00:00
Dan Gohman 643b3a0581 Add #includes to make some dependencies explicit. 
llvm-svn: 51496
 2008-05-23 20:40:06 +00:00
Dan Gohman 6d5f120c5c Generalize the new code in instcombine's ComputeNumSignBits for handling 
and/or to handle more cases (such as this add-sitofp.ll testcase), and
port it to selectiondag's ComputeNumSignBits.

llvm-svn: 51469
 2008-05-23 02:28:01 +00:00
Dan Gohman 396ed504f1 Use isSingleValueType instead of isFirstClassType to 
exclude struct and array types.

llvm-svn: 51460
 2008-05-23 00:34:04 +00:00
Dan Gohman fe13618682 Port the fix for the select operator from instcombine's 
ComputeNumSignBits to SelectionDAG's ComputeNumSignBits.

llvm-svn: 51348
 2008-05-20 20:59:51 +00:00
Dan Gohman c1a4e212a3 Code simplification. 
llvm-svn: 51345
 2008-05-20 20:56:33 +00:00
Evan Cheng 9ac3631fa3 If the result of a BIT_CONVERT is a v1* vector, it doesn't mean its source is a v1* vector. 
llvm-svn: 51192
 2008-05-16 17:19:05 +00:00
Duncan Sands 70424d195a Silence the compiler warning differently. The 
original method caused gcc-4.2 to complain.

llvm-svn: 51186
 2008-05-16 09:19:16 +00:00
Nate Begeman f79f52282c Actually scalarize the operand to BIT_CONVERT instead of asking someone to do 
something with a v1 type.

llvm-svn: 51160
 2008-05-15 20:40:58 +00:00
Dan Gohman 12fce7751b IR support for extractvalue and insertvalue instructions. Also, begin 
moving toward making structs and arrays first-class types.

llvm-svn: 51157
 2008-05-15 19:50:34 +00:00
Evan Cheng ef377adca0 Make use of vector load and store operations to implement memcpy, memmove, and memset. Currently only X86 target is taking advantage of these. 
llvm-svn: 51140
 2008-05-15 08:39:06 +00:00
Evan Cheng 4ea9d49590 Use a better idiom to silence compiler warnings. 
llvm-svn: 51131
 2008-05-14 21:08:07 +00:00
Evan Cheng 0f7fb95e79 Really silence compiler warnings. 
llvm-svn: 51126
 2008-05-14 20:29:30 +00:00
Evan Cheng a5b0a8d7fe Really silence compiler warnings. 
llvm-svn: 51123
 2008-05-14 20:26:35 +00:00
Evan Cheng 763ec13862 Silence some compiler warnings. 
llvm-svn: 51115
 2008-05-14 20:07:51 +00:00
Dan Gohman 3ab94df276 When bit-twiddling CondCode values for integer comparisons produces 
SETOEQ, is it does with (SETEQ & SETULE), map it to SETEQ.

llvm-svn: 51112
 2008-05-14 18:17:09 +00:00
Dan Gohman fd3e3003f3 Whitespace cleanups. 
llvm-svn: 51089
 2008-05-14 00:43:10 +00:00
Evan Cheng 1120279ae6 Instead of a vector load, shuffle and then extract an element. Load the element from address with an offset. 
pshufd $1, (%rdi), %xmm0
        movd %xmm0, %eax
=>
        movl 4(%rdi), %eax

llvm-svn: 51026
 2008-05-13 08:35:03 +00:00
Dan Gohman d78c400b5b Clean up the use of static and anonymous namespaces. This turned up 
several things that were neither in an anonymous namespace nor static
but not intended to be global.

llvm-svn: 51017
 2008-05-13 00:00:25 +00:00
Nate Begeman b87e63a730 Teach Legalize how to scalarize VSETCC 
Teach X86 a few more vsetcc patterns.  Custom lowering for unsupported ones is next.

llvm-svn: 51009
 2008-05-12 23:09:43 +00:00
Evan Cheng b980f6fb3d Xform bitconvert(build_pair(load a, load b)) to a single load if the load locations are at the right offset from each other. 
llvm-svn: 51008
 2008-05-12 23:04:07 +00:00
Evan Cheng 2609d5e779 Refactor isConsecutiveLoad from X86 to TargetLowering so DAG combiner can make use of it. 
llvm-svn: 50991
 2008-05-12 19:56:52 +00:00
Nate Begeman cfcb56091b Add support for vicmp/vfcmp codegen, more legalize support coming. 
This is necessary to unbreak the build.

llvm-svn: 50988
 2008-05-12 19:40:03 +00:00
Dan Gohman ecb77385ab Fix a missing break in the ISD::FLT_ROUNDS_ handling. Patch by giuma! 
llvm-svn: 50967
 2008-05-12 16:07:15 +00:00
Anton Korobeynikov fc2edad4ae Turn StripPointerCast() into a method 
llvm-svn: 50836
 2008-05-07 22:54:15 +00:00
Dan Gohman 5a3eecdfd8 Fix a bug in the ComputeMaskedBits logic for multiply. 
llvm-svn: 50793
 2008-05-07 00:35:55 +00:00
Anton Korobeynikov 82c02b28f3 Make StripPointerCast a common function (should we mak it method of Value instead?) 
llvm-svn: 50775
 2008-05-06 22:52:30 +00:00
Dan Gohman 6a2da37c0e Make several variable declarations static. 
llvm-svn: 50696
 2008-05-06 01:53:16 +00:00
Dan Gohman 38dc08f36f Instead of enumerating each opcode that isn't handled that 
ComputeMaskedBits handles, just use a 'default:'. This avoids
TargetLowering's list getting out of date with SelectionDAG's.

llvm-svn: 50693
 2008-05-06 00:53:29 +00:00
Dan Gohman cf0e3acf16 Correct the value of LowBits in srem and urem handling in 
ComputeMaskedBits.

llvm-svn: 50692
 2008-05-06 00:51:48 +00:00
Mon P Wang 3e58393c3d Added addition atomic instrinsics and, or, xor, min, and max. 
llvm-svn: 50663
 2008-05-05 19:05:59 +00:00
Dan Gohman 1962c2be6a Fix a mistake in the computation of leading zeros for udiv. 
llvm-svn: 50591
 2008-05-02 21:30:02 +00:00
Dan Gohman 2f83b47863 Fix a typo in a comment. 
llvm-svn: 50562
 2008-05-02 00:05:03 +00:00
Dan Gohman ea6357828b Use push_back(...) instead of resize(1, ...), per review feedback. 
llvm-svn: 50561
 2008-05-02 00:03:54 +00:00
Dan Gohman 752ce50b2d Fix uninitialized uses of the FPC variable. 
llvm-svn: 50558
 2008-05-01 23:40:44 +00:00
Chris Lattner d4b2a67cf3 don't randomly miscompile seto/setuo just because we are in 
ffastmath mode.  This fixes rdar://5902801, a miscompilation
of gcc.dg/builtins-8.c.

Bill, please pull this into Tak.

llvm-svn: 50523
 2008-05-01 07:26:11 +00:00
Arnold Schwaighofer be0de34ede Tail call optimization improvements: 
Move platform independent code (lowering of possibly overwritten
arguments, check for tail call optimization eligibility) from
target X86ISelectionLowering.cpp to TargetLowering.h and
SelectionDAGISel.cpp.

Initial PowerPC tail call implementation:

Support ppc32 implemented and tested (passes my tests and
test-suite llvm-test).  
Support ppc64 implemented and half tested (passes my tests).
On ppc tail call optimization is performed if 
  caller and callee are fastcc
  call is a tail call (in tail call position, call followed by ret)
  no variable argument lists or byval arguments
  option -tailcallopt is enabled
Supported:
 * non pic tail calls on linux/darwin
 * module-local tail calls on linux(PIC/GOT)/darwin(PIC)
 * inter-module tail calls on darwin(PIC)
If constraints are not met a normal call will be emitted.

A test checking the argument lowering behaviour on x86-64 was added.

llvm-svn: 50477
 2008-04-30 09:16:33 +00:00
Scott Michel be940424b3 Fix custom target lowering for zero/any/sign_extend: make sure that 
DAG.UpdateNodeOperands() is called before (not after) the call to
TLI.LowerOperation().

llvm-svn: 50461
 2008-04-30 00:26:38 +00:00
Roman Levenstein 6b37114590 Use std::set instead of std::priority_queue for the RegReductionPriorityQueue. 
This removes the existing bottleneck related to the removal of elements from 
the middle of the queue.

Also fixes a subtle bug in ScheduleDAGRRList::CapturePred:
It was updating the state of the SUnit before removing it. As a result, the
comparison operators were working incorrectly and this SUnit could not be removed 
from the queue properly.

Reviewed by Evan and Dan. Approved by Dan.

llvm-svn: 50412
 2008-04-29 09:07:59 +00:00
Chris Lattner 5c88f7b1ad make the vector conversion magic handle multiple results. 
We now compile test2/test3 to:

_test2:
	## InlineAsm Start
	set %xmm0, %xmm1
	## InlineAsm End
	addps	%xmm1, %xmm0
	ret
_test3:
	## InlineAsm Start
	set %xmm0, %xmm1
	## InlineAsm End
	paddd	%xmm1, %xmm0
	ret

as expected.

llvm-svn: 50389
 2008-04-29 04:48:56 +00:00
Chris Lattner f9a49c4322 add support for multiple return values in inline asm. This is a step 
towards PR2094.  It now compiles the attached .ll file to:

_sad16_sse2:
	movslq	%ecx, %rax
	## InlineAsm Start
	%ecx %rdx %rax %rax %r8d %rdx %rsi
	## InlineAsm End
	## InlineAsm Start
	set %eax
	## InlineAsm End
	ret

which is pretty decent for a 3 output, 4 input asm.

llvm-svn: 50386
 2008-04-29 04:29:54 +00:00
Evan Cheng b96782ecbd Fix a bug in RegsForValue::getCopyToRegs() that causes cyclical scheduling units. If it's creating multiple CopyToReg nodes that are "flagged" together, it should not create a TokenFactor for it's chain outputs: 
c1, f1 = CopyToReg                                                                                                                                                                                             
c2, f2 = CopyToReg                                                                                                                                                                                             
c3     = TokenFactor c1, c2                                                                                                                                                                                    
 ...                                                                                                                                                                                                                      
       = user c3, ..., f2

Now that the two CopyToReg's and the user are "flagged" together. They effectively forms a single scheduling unit. The TokenFactor is now both an operand and a successor of the Flagged nodes.

llvm-svn: 50376
 2008-04-28 22:07:13 +00:00
Dan Gohman c968c1f592 Evan pointed out that folding sext to zext may not be correct 
if the zext is not legal.

llvm-svn: 50368
 2008-04-28 18:47:17 +00:00
Dan Gohman 77ce6da378 Delete an unused constructor. 
llvm-svn: 50367
 2008-04-28 18:28:49 +00:00