f1a5f57d2f
Fix typo in comment.
...
llvm-svn: 139122
2011-09-05 18:35:03 +00:00
34842ceb97
Thumb2 parsing and encoding for BXJ.
...
llvm-svn: 139053
2011-09-02 23:43:09 +00:00
a0d34d3b5e
Thumb2 parsing and encoding of B instruction.
...
Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.
llvm-svn: 139049
2011-09-02 23:22:08 +00:00
f3dd6da7a8
Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel.
...
llvm-svn: 139044
2011-09-02 22:33:24 +00:00
a216debb37
Thumb2 parsing and encoding for ASR.
...
For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.
llvm-svn: 139040
2011-09-02 21:28:54 +00:00
05dec8b122
Tidy up. Formatting.
...
llvm-svn: 139024
2011-09-02 18:46:15 +00:00
0a57375a28
Tidy up. 80 columns.
...
llvm-svn: 139022
2011-09-02 18:43:25 +00:00
370e923434
Thumb2 parsing and encoding for AND (register).
...
llvm-svn: 139021
2011-09-02 18:41:35 +00:00
2761155203
Thumb2 parsing and encoding for ADD (register).
...
llvm-svn: 139017
2011-09-02 18:14:46 +00:00
ed96b58bd2
Merge the ARM disassembler header into the implementation file, since it is not externally exposed.
...
llvm-svn: 138982
2011-09-01 23:35:51 +00:00
03aadae01f
Fix 80 columns violations.
...
llvm-svn: 138980
2011-09-01 23:23:50 +00:00
6397051ece
Don't drop alignment info on local common symbols.
...
- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm
Based on a patch by NAKAMURA Takumi.
Fixes PR9337, PR9483 and PR10128.
llvm-svn: 138976
2011-09-01 23:04:27 +00:00
d7776ed030
Null-initialize to shut up -Wuninitialized warnings.
...
llvm-svn: 138974
2011-09-01 22:27:41 +00:00
f6d5d60f99
ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code.
...
llvm-svn: 138952
2011-09-01 18:22:13 +00:00
db4ce60328
Fix up r137380 based on post-commit review by Jim Grosbach.
...
llvm-svn: 138948
2011-09-01 18:02:14 +00:00
35d240f9e8
t2Bcc is allowed to have a predicate without a preceding IT instruction.
...
llvm-svn: 138946
2011-09-01 17:47:45 +00:00
1d3c137839
Thumb2 assembly parsing and encoding for ADD(immediate).
...
llvm-svn: 138922
2011-09-01 00:28:52 +00:00
17847ae757
Fixup for functions that return a bool.
...
llvm-svn: 138918
2011-08-31 23:49:05 +00:00
e1995f2566
Static relocation model Thumb jump table interworking.
...
Make sure the low bit of the PC is set when loading an address directly
for jump tables in static relocation model.
llvm-svn: 138912
2011-08-31 22:23:09 +00:00
4af0aa98d5
The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps.
...
llvm-svn: 138910
2011-08-31 22:00:41 +00:00
99bc84662f
Thumb2 t2Bcc should encode as t2B when condition is 'always'.
...
llvm-svn: 138898
2011-08-31 21:17:31 +00:00
a455a0b1e7
Fix encoding for tBcc with immediate offset operand.
...
llvm-svn: 138889
2011-08-31 20:26:14 +00:00
939cd21248
When performing instruction selection for LDR_PRE_IMM/LDRB_PRE_IMM, we still need to preserve the sign of the index. This fixes miscompilations of Quicksort in the nightly testsuite, and hopefully others as well.
...
<rdar://problem/10046188>
llvm-svn: 138885
2011-08-31 20:00:11 +00:00
cfa9421e16
Remove FIXME. Thumb2 MOV instruction will use separate custom tricks.
...
When we want encoding T3 (the wide encoding), we can explicitly check for
that and twiddle the CanAcceptCarrySet accordingly. For now, just correctly
handle encodings T1 and T2 when in Thumb2 mode.
llvm-svn: 138879
2011-08-31 18:39:39 +00:00
5c160fd243
Fix roundtripping of Thumb BL/BLX instructions with immediate offsets instead of labels.
...
llvm-svn: 138874
2011-08-31 18:30:20 +00:00
c61fc8f301
tBcc is OK to be predicated in Thumb2 outside of IT blocks (obviously).
...
llvm-svn: 138873
2011-08-31 18:29:05 +00:00
af8c3cc710
Thumb2 parsing and encoding for ADC(register).
...
Also add instruction aliases for non-.w versions of SBC since they're the
same.
llvm-svn: 138871
2011-08-31 18:23:08 +00:00
1ccecbb9d3
64-bit atomic cmpxchg for ARM.
...
llvm-svn: 138868
2011-08-31 17:52:22 +00:00
6d606fbe14
Tweak Thumb1 ADD encoding selection a bit.
...
When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.
llvm-svn: 138862
2011-08-31 17:07:33 +00:00
cd893390f5
Put VMOVS widening under a command line option, off by default.
...
It appears that our use of the imp-use and imp-def flags with
sub-registers is not yet robust enough to support this.
The failing test case is complicated, I am working on a reduction.
<rdar://problem/10044201>
llvm-svn: 138861
2011-08-31 17:00:02 +00:00
2c7bb52f56
Some minor cleanups for r138845.
...
llvm-svn: 138846
2011-08-31 00:41:05 +00:00
c3f9c4a852
Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next.
...
llvm-svn: 138845
2011-08-31 00:31:29 +00:00
2fa06a7226
Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing.
...
llvm-svn: 138840
2011-08-30 22:58:27 +00:00
fdf3cd7f2b
Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather than labels.
...
llvm-svn: 138837
2011-08-30 22:15:17 +00:00
d16fb43b1f
Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets instead of labels.
...
llvm-svn: 138835
2011-08-30 22:10:03 +00:00
543c89fb15
Fix encoding of Thumb1 B instructions with immediate offsets, which is necessary for round-tripping.
...
llvm-svn: 138834
2011-08-30 22:03:20 +00:00
1732c2ebf6
Clean up whitespace.
...
llvm-svn: 138833
2011-08-30 21:58:18 +00:00
e6fba77971
Follow up to r138791.
...
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.
llvm-svn: 138810
2011-08-30 19:09:48 +00:00
e891654a58
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical
...
register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.
When a i64 sub is expanded to subc + sube.
libcall #1
\
\ subc
\ / \
\ / \
\ / libcall #2
sube
If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.
subc
|
libcall #2
|
libcall #1
|
sube
However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.
The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.
rdar://10019576
llvm-svn: 138791
2011-08-30 01:34:54 +00:00
6e59d5c916
Revert 138781. It's not playing nicely with the immediate forms for ADC.
...
llvm-svn: 138782
2011-08-29 23:24:15 +00:00
19a75f075d
Thumb2 assembler aliases for ADC/SBC w/o the .w suffix.
...
llvm-svn: 138781
2011-08-29 23:20:54 +00:00
3e0aa03fe9
Add missing encoding information for some of the GPR<->FP register moves.
...
llvm-svn: 138780
2011-08-29 23:15:25 +00:00
ed16ec4248
Thumb2 parsing and encoding for IT blocks.
...
llvm-svn: 138773
2011-08-29 22:24:09 +00:00
243274c789
Apply the same fix for the change in LDR_PRE_IMM/LDRB_PRE_IMM operand encodings to the load-store optimizer that I applied to the instruction selector in r138758. Fixes ary3 from the nightly test suite.
...
llvm-svn: 138766
2011-08-29 21:14:19 +00:00
32ac76616e
Specify an additional fixed bit in the PLD/PLDW/PLI register-register encoding.
...
llvm-svn: 138760
2011-08-29 20:42:00 +00:00
4d5c8f894d
addrmode_imm12 and addrmode2_offset encode their immediate values differently. Update the manual instruction selection code that was encoding them the addrmode2 way even though LDR_PRE_IMM/LDRB_PRE_IMM had switched to addrmode_imm12. Should fix a number of nightly test failures.
...
llvm-svn: 138758
2011-08-29 20:16:50 +00:00
967674d26c
Improve handling of #-0 offsets for many more pre-indexed addressing modes.
...
llvm-svn: 138754
2011-08-29 19:36:44 +00:00
7dfa791f4f
Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly.
...
llvm-svn: 138751
2011-08-29 18:23:02 +00:00
6314343333
Update the load-store optimizer for changes to the operands on LDR_PRE_IMM and LDRB_PRE_IMM in r138653.
...
llvm-svn: 138746
2011-08-29 17:59:41 +00:00
f02d98d7c0
Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it.
...
llvm-svn: 138739
2011-08-29 17:17:09 +00:00
61a1ff543c
Silence GCC warnings and make an array const.
...
llvm-svn: 138706
2011-08-27 17:36:14 +00:00
b205c029a4
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
...
llvm-svn: 138675
2011-08-26 23:32:08 +00:00
6c70e58041
Correct encoding of BL with immediate offset.
...
llvm-svn: 138673
2011-08-26 22:54:51 +00:00
b9d4e37776
ARM assembly parsing tweak for pldw.
...
llvm-svn: 138669
2011-08-26 22:21:51 +00:00
240d20af79
Spelling fail.
...
llvm-svn: 138667
2011-08-26 21:47:57 +00:00
3d1eac85c3
Thumb2 assembler parsing and encoding of IT instruction.
...
This handles only the handling of the IT instruction itself, not the
processing and validation of the instructions in the IT block. That's next,
and will include encoding tests for IT itself.
llvm-svn: 138665
2011-08-26 21:43:41 +00:00
fd60f60ed1
Fix ARM codegen breakage caused by r138653.
...
llvm-svn: 138657
2011-08-26 21:12:37 +00:00
16d33f36d5
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.
...
llvm-svn: 138653
2011-08-26 20:43:14 +00:00
5658b49f64
Update for feedback from Jim.
...
llvm-svn: 138642
2011-08-26 19:39:26 +00:00
aa38dbadca
ARMDisassembler: Always return a size, even when disassembling fails.
...
This should fix PR10772.
llvm-svn: 138636
2011-08-26 18:21:36 +00:00
a01bcbfc80
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
...
llvm-svn: 138635
2011-08-26 18:09:22 +00:00
149695627a
Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors.
...
This is the last disassembly crash detected by exhaustive Thumb2 instruction space. Major thanks to Chandler Carruth for making this kind of exhaustive testing possible.
llvm-svn: 138625
2011-08-26 06:19:51 +00:00
452aae6202
Atomic load/store on ARM/Thumb.
...
I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.
I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.
llvm-svn: 138621
2011-08-26 02:59:24 +00:00
64bfca1b60
Remove stray fullstop.
...
llvm-svn: 138589
2011-08-25 21:46:20 +00:00
5e30972cff
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
...
llvm-svn: 138575
2011-08-25 18:30:18 +00:00
6446bf780a
ARM fix for missing implicit operands on ldmia_ret.
...
rdar://10005094: miscompile of 176.gcc
llvm-svn: 138568
2011-08-25 17:50:53 +00:00
f7ecc16c96
whitespace
...
llvm-svn: 138566
2011-08-25 17:40:54 +00:00
1c171b121a
Explicitly disallow predication in Thumb1 assembly.
...
llvm-svn: 138562
2011-08-25 17:23:55 +00:00
9dad430486
Hide -global-merge option.
...
llvm-svn: 138540
2011-08-25 01:22:49 +00:00
f066b2fe99
Add a command line option to disable global merge pass.
...
llvm-svn: 138536
2011-08-25 01:00:36 +00:00
3ca20e64ac
Remove a out-of-place comment.
...
llvm-svn: 138534
2011-08-25 00:54:42 +00:00
37612a3de3
Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space.
...
llvm-svn: 138507
2011-08-24 22:40:22 +00:00
21a60b6f90
ARM asm backend initialize isThumbMode based on target triple.
...
llvm-svn: 138501
2011-08-24 22:27:35 +00:00
838ed3af46
Thumb .n mnemonic qualifiers can be ignored for now.
...
We'll need to pay attention to them when we start getting more serious about
the details of parsing thumb2 assembly.
llvm-svn: 138500
2011-08-24 22:19:48 +00:00
4b701af908
Thumb parsing and encoding for SUB (SP minu immediate).
...
Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.
llvm-svn: 138494
2011-08-24 21:42:27 +00:00
216cfaa808
Be careful not to walk off the end of the operand info list while updating VFP predicates.
...
llvm-svn: 138492
2011-08-24 21:35:46 +00:00
0a0b3071df
Thumb parsing and encoding support for ADD SP instructions.
...
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.
llvm-svn: 138488
2011-08-24 21:22:15 +00:00
af2f827a2c
When printing Thumb1 NOP ('mov r8, r8'), make sure to print the predicate.
...
rdar://10015134
llvm-svn: 138467
2011-08-24 20:06:14 +00:00
6ccd79f4d5
Add missing explicit writeback operand to tSTMIA_UPD.
...
rdar://10014745
llvm-svn: 138457
2011-08-24 18:19:42 +00:00
2bb4035707
Move TargetRegistry and TargetSelect from Target to Support where they belong.
...
These are strictly utilities for registering targets and components.
llvm-svn: 138450
2011-08-24 18:08:43 +00:00
a281f2d07d
Thumb add SP assembly syntax fix.
...
llvm-svn: 138448
2011-08-24 18:04:27 +00:00
1b8457a84c
Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.
...
Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.
llvm-svn: 138445
2011-08-24 17:46:13 +00:00
523004145e
Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate.
...
llvm-svn: 138443
2011-08-24 17:21:43 +00:00
51b554247d
Move ARM frame-unwinding EHABI handling a touch earlier.
...
It should go before AsmPrinter MC pseudo expansion since it's based on
MachineInstr, not MCInst. Otherwise any frame related pseudo instructions
may be missed.
llvm-svn: 138386
2011-08-23 21:32:34 +00:00
50b0f6669c
[SU]XT[BH] are only available on ARMv6 and up.
...
llvm-svn: 138373
2011-08-23 20:53:08 +00:00
4d6c9d711d
Some refactoring so TargetRegistry.h no longer has to include any files
...
from MC.
llvm-svn: 138367
2011-08-23 20:15:21 +00:00
5cc338da67
Thumb parsing and encoding for SVC.
...
llvm-svn: 138360
2011-08-23 19:49:10 +00:00
505be75900
Thumb parsing and encoding for tSTRspi.
...
llvm-svn: 138348
2011-08-23 18:39:41 +00:00
d80d169a04
Thumb parsing and encoding for STM.
...
llvm-svn: 138345
2011-08-23 18:15:37 +00:00
169b2be611
Factor low reg checking into a helper function.
...
llvm-svn: 138344
2011-08-23 18:13:04 +00:00
924bcfc92f
Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.
...
llvm-svn: 138341
2011-08-23 17:51:38 +00:00
9b7bd15d0b
Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions.
...
llvm-svn: 138339
2011-08-23 17:45:18 +00:00
e364ad540a
Clean up Thumb load/store multiple definitions.
...
There is no non-writeback store multiple instruction in Thumb1, so
don't define one. As a result load multiple is the only instantiation of
the multiclass, so refactor that away entirely.
llvm-svn: 138338
2011-08-23 17:41:15 +00:00
041dba6dec
Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing.
...
llvm-svn: 138337
2011-08-23 17:37:32 +00:00
3636be3c8f
Thumb parsing and encoding for SBC.
...
llvm-svn: 138311
2011-08-22 23:55:58 +00:00
c3c32d9e09
Thumb parsing and encoding for RSB.
...
llvm-svn: 138308
2011-08-22 23:47:13 +00:00
eb1367b2b8
Reject invalid imod values in t2CPS instructions.
...
llvm-svn: 138306
2011-08-22 23:44:04 +00:00
1346d79b4b
t2SMLAD is a four-register instruction, not a three-register one.
...
llvm-svn: 138301
2011-08-22 23:31:45 +00:00
f94b7b7d57
Correct operand naming of t2USAT16 to allow proper decoding.
...
llvm-svn: 138300
2011-08-22 23:27:47 +00:00
bfeb4f78af
Revert r138278 now that r138289 has fixed the root issue.
...
llvm-svn: 138299
2011-08-22 23:25:48 +00:00
5e9989a920
Match operand naming to allow correct decoding of t2LDRSH_POST.
...
llvm-svn: 138298
2011-08-22 23:22:05 +00:00
38c59fcb08
Improve error checking for tPUSH and tPOP register lists.
...
llvm-svn: 138295
2011-08-22 23:17:34 +00:00
2844a81079
Match operand names to provide correct decoding for Thumb2 SMULL.
...
llvm-svn: 138294
2011-08-22 23:16:48 +00:00
a743409ec8
Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing.
...
llvm-svn: 138292
2011-08-22 23:10:16 +00:00
139acd21e6
Thumb assemmbly parsing diagnostic improvements for LDM.
...
llvm-svn: 138287
2011-08-22 23:01:07 +00:00
ca2ffad8b1
Temporarilly mark tMUL as not commutable.
...
It's not playing nicely in the coalescer with the tied operand. Disable
commutability for now while we figure out the deeper fix.
llvm-svn: 138278
2011-08-22 22:00:18 +00:00
061738a680
Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing.
...
llvm-svn: 138273
2011-08-22 21:34:00 +00:00
df698b032c
Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.
...
llvm-svn: 138269
2011-08-22 20:27:12 +00:00
5c932b24be
Tighten up ARM reglist validation a bit.
...
llvm-svn: 138258
2011-08-22 18:50:36 +00:00
721c3704da
Fix another batch of VLD/VST decoding crashes discovered by randomized testing.
...
llvm-svn: 138255
2011-08-22 18:42:13 +00:00
ac92e77bb8
Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing.
...
llvm-svn: 138251
2011-08-22 18:22:06 +00:00
6caa557ae6
Clean up predicates on ARM target instruction aliases.
...
llvm-svn: 138249
2011-08-22 18:04:24 +00:00
b49813206b
Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests.
...
llvm-svn: 138246
2011-08-22 17:56:58 +00:00
61f92efb5c
Remove the VMOVQQ pseudo instruction.
...
llvm-svn: 138177
2011-08-20 00:52:40 +00:00
baf5538da9
Remove VMOVQQQQ pseudo instruction.
...
llvm-svn: 138174
2011-08-20 00:40:14 +00:00
59015c8b17
Add <imp-def> operands to QQ and QQQQ stack loads.
...
This pleases the register scavenger and brings
test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll a little closer to
working with -verify-machineinstrs.
llvm-svn: 138164
2011-08-20 00:17:45 +00:00
be7625161e
VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg.
...
Therefore, rather then generate a pseudo instruction, which is later expanded,
generate the necessary instructions in place.
llvm-svn: 138163
2011-08-20 00:17:25 +00:00
2597722e07
Thumb parsing and encoding support for NOP.
...
The irony is not lost that this is not a completely trivial patchset.
llvm-svn: 138143
2011-08-19 23:24:36 +00:00
37aa348195
Thumb assembly parsing and encoding for NEG.
...
llvm-svn: 138131
2011-08-19 22:51:03 +00:00
8022015a16
Fix NEG alias
...
llvm-svn: 138125
2011-08-19 22:30:58 +00:00
459422d750
Be more lenient on tied operand matching for MUL.
...
llvm-svn: 138124
2011-08-19 22:30:46 +00:00
066e9ec1e4
Update tests.
...
llvm-svn: 138116
2011-08-19 22:19:48 +00:00
8e048495c8
Thumb assembly parsing and encoding for MUL.
...
llvm-svn: 138108
2011-08-19 22:07:46 +00:00
f86cd37bef
Thumb assembly parsing and encoding for MOV.
...
llvm-svn: 138076
2011-08-19 20:46:54 +00:00
dbb60f960a
Tidy up. Tab character.
...
llvm-svn: 138072
2011-08-19 20:30:19 +00:00
9c92049069
Tab characters.
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llvm-svn: 138066
2011-08-19 19:41:46 +00:00
5503c3a4e8
Thumb assembly parsing and encoding for LSL(immediate).
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llvm-svn: 138063
2011-08-19 19:29:25 +00:00
7c4739da3c
Thumb assembly parsing and encoding for LDRSB and LDRSH.
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llvm-svn: 138061
2011-08-19 19:17:58 +00:00
26d3587bd8
Thumb assembly parsing and encoding for LDRH.
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llvm-svn: 138060
2011-08-19 18:55:51 +00:00
a32c753ebf
Thumb assembly parsing and encoding for LDRB.
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llvm-svn: 138059
2011-08-19 18:49:59 +00:00
181d2f92b5
Thumb assembly parsing and encoding for LDR(literal).
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llvm-svn: 138052
2011-08-19 18:20:48 +00:00
23983d6bd9
Thumb assembly parsing and encoding for LDR(immediate) form T2.
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llvm-svn: 138050
2011-08-19 18:13:48 +00:00
7473329725
Use helper function to check for low registers.
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llvm-svn: 138048
2011-08-19 17:57:22 +00:00
3fe94e3ef8
Thumb assembly parsing and encoding for LDR(immediate) form T1.
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llvm-svn: 138047
2011-08-19 17:55:24 +00:00
e93807049b
Add explanatory comment.
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llvm-svn: 138042
2011-08-19 16:52:32 +00:00
4938edb02c
Make a bunch of symbols private.
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llvm-svn: 138025
2011-08-19 01:42:18 +00:00
96b7ad2e17
STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate.
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Found by randomized testing.
llvm-svn: 138003
2011-08-18 22:47:44 +00:00
192a760b54
Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset.
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llvm-svn: 138000
2011-08-18 22:31:17 +00:00
5d2db89ba6
Remember to fill in some operands so we can print _something_ coherent even when decoding the CPS instruction soft-fails.
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llvm-svn: 137997
2011-08-18 22:15:25 +00:00
67d6f11974
Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions.
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Fixes a large class of disassembler crashes found by randomized testing.
llvm-svn: 137995
2011-08-18 22:11:02 +00:00
90103ccc05
Thumb assembly parsing and encoding for LDM instruction.
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Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.
llvm-svn: 137986
2011-08-18 21:50:53 +00:00
4f240a1fd5
Thumb assembly parsing and encoding for CMP.
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llvm-svn: 137963
2011-08-18 18:08:29 +00:00
8a6bed863a
Thumb instructions CBZ and CBNZ are Thumb2, not THumb1.
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llvm-svn: 137956
2011-08-18 17:51:36 +00:00
f00b9ccd22
ARM Thumb blx instruction fixup has same data range as bl.
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These fixups are handled poorly in general, and should have a single
contiguous range of bits per fixup type, but that's not how they're
currently organized, so for now in complex ones like for blx, we just tell the
emitter it's OK for the fixup to munge any bit it wants.
llvm-svn: 137947
2011-08-18 16:57:50 +00:00
8fa3f6a2b4
80 columns.
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llvm-svn: 137946
2011-08-18 16:50:45 +00:00
6ddb568ab8
Add missing 'break'.
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llvm-svn: 137941
2011-08-18 16:08:39 +00:00
50aafeaa2c
Remove extraneous newline from operand print method. PR10569.
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llvm-svn: 137900
2011-08-17 23:23:07 +00:00
23b729eeba
Clean up patterns for Thumb1 system instructions.
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llvm-svn: 137897
2011-08-17 23:08:57 +00:00
cbd4ab104b
Thumb assembly parsing and encoding for B.
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llvm-svn: 137891
2011-08-17 22:57:40 +00:00
d3e8e29124
Thumb assembly parsing and encoding for ASR.
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llvm-svn: 137889
2011-08-17 22:49:09 +00:00
d14b70d00b
Tidy up. 80 columns.
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llvm-svn: 137881
2011-08-17 21:58:18 +00:00
46dd413991
ARM clean up the imm_sr operand class representation.
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Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.
llvm-svn: 137879
2011-08-17 21:51:27 +00:00
854fe433d4
Fix predicate for imm1_32
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llvm-svn: 137865
2011-08-17 21:01:11 +00:00
e2a0404a69
Thumb assembly parsing and encoding for ADR.
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llvm-svn: 137864
2011-08-17 20:37:40 +00:00
3b5a69cc45
80 columns.
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llvm-svn: 137857
2011-08-17 19:55:51 +00:00
8637523886
Tidy up.
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llvm-svn: 137856
2011-08-17 19:53:53 +00:00
187e1e46f9
Be more careful in the Thumb decoder hooks to avoid walking off the end of the OpInfo array.
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llvm-svn: 137838
2011-08-17 18:14:48 +00:00
a4043c4b32
Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
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Patch by James Molloy.
llvm-svn: 137830
2011-08-17 17:44:15 +00:00
e9ab47a72a
Thumb ADD(immediate) parsing support.
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llvm-svn: 137788
2011-08-16 23:57:34 +00:00
91a8f9be20
Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them.
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llvm-svn: 137787
2011-08-16 23:45:44 +00:00
b7fa2c0a53
Thumb parsing diagnostics for low-reg requirements on ADD and MOV.
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llvm-svn: 137779
2011-08-16 22:20:01 +00:00
64610e52e7
Add missing exit for 'case'.
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llvm-svn: 137774
2011-08-16 21:42:31 +00:00
58ffdccab1
Thumb assembly parsing and encoding for ADD(register) instruction.
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llvm-svn: 137759
2011-08-16 21:34:08 +00:00
7283da9bb2
Move some logic into a helper function and expand the commentary.
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llvm-svn: 137756
2011-08-16 21:12:37 +00:00
3e941aee69
ARM thumb assembly parsing for arithmetic flag setting instructions.
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Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.
llvm-svn: 137746
2011-08-16 20:45:50 +00:00
45e50d8a0b
ARM .align NOP padding uses different encoding pre-ARMv6.
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Patch by Kristof Beyls and James Malloy.
llvm-svn: 137723
2011-08-16 17:06:20 +00:00
a6201f0a72
Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness.
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llvm-svn: 137686
2011-08-15 23:38:54 +00:00
120a96a721
MCTargetAsmParser target match predicate support.
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Allow a target assembly parser to do context sensitive constraint checking
on a potential instruction match. This will be used, for example, to handle
Thumb2 IT block parsing.
llvm-svn: 137675
2011-08-15 23:03:29 +00:00
1d5d2cac8c
Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
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Patch by James Molloy.
llvm-svn: 137647
2011-08-15 20:51:32 +00:00
de25f9aa8f
Remove dead classes.
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llvm-svn: 137643
2011-08-15 20:11:11 +00:00
61a3ece665
Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
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llvm-svn: 137641
2011-08-15 20:08:25 +00:00
3157f2eebe
Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.
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llvm-svn: 137636
2011-08-15 19:00:06 +00:00
b9d82f411c
Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
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llvm-svn: 137635
2011-08-15 18:44:44 +00:00
30694dcdeb
Update comment to reflect MC target machine refactor.
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llvm-svn: 137615
2011-08-15 16:52:24 +00:00
d1de7764be
Expand VMOVQQQQ pseudo instructions.
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Apparently we never added code to expand these pseudo instructions, and in
over a year, no one has noticed. Our register allocator must be awesome!
llvm-svn: 137551
2011-08-13 05:14:55 +00:00
2325474368
ARM STR_POST_IMM offset encoding fix in load/store optimizer.
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Tidy up the code a bit and push the definition of the value next to the uses
to try to minimize this sort of issue from arising again while I'm at it.
rdar://9945172
llvm-svn: 137525
2011-08-12 22:20:41 +00:00
f402f694e2
ARM expansion of pre-indexed store pseudos should maintain memoperands.
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Partial fix for rdar://9945172.
llvm-svn: 137513
2011-08-12 21:02:34 +00:00
2d1d7a11f8
Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
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llvm-svn: 137502
2011-08-12 20:36:11 +00:00
60138eaf93
Fix decoding of ARM-mode STRH.
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llvm-svn: 137499
2011-08-12 20:02:50 +00:00
1043e173bc
Specify fixed bit in the LDRBT encoding, which allows us to distinguish it from certain USAT16 encodings.
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llvm-svn: 137494
2011-08-12 19:41:29 +00:00
3987a61c16
Fix decoding of pre-indexed stores.
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llvm-svn: 137487
2011-08-12 18:12:39 +00:00
c5798a3a59
Separate decoding for STREXD and LDREXD to make each work better.
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llvm-svn: 137476
2011-08-12 17:58:32 +00:00
a41634e307
Silence a bunch (but not all) "variable written but not read" warnings
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when building with assertions disabled.
llvm-svn: 137460
2011-08-12 14:54:45 +00:00
8cffa28af8
ARM vector compare to zero instruction assembly parsing support.
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llvm-svn: 137389
2011-08-11 23:51:13 +00:00
37f7e6b2f4
Remove no-longer-true comments. These are for the assembler, also.
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llvm-svn: 137375
2011-08-11 22:30:30 +00:00
e25942154c
ARM STRT assembly parsing and encoding.
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llvm-svn: 137372
2011-08-11 22:18:00 +00:00
eca346ee1a
Make the USAT16 operand decoder auto-generate-able.
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llvm-svn: 137371
2011-08-11 22:10:11 +00:00
ff0b442330
Add another accidentally omitted predicate operand.
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llvm-svn: 137370
2011-08-11 22:08:38 +00:00
2f7aa73312
Add missing predicate operand on SMLA and friends.
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llvm-svn: 137368
2011-08-11 22:05:38 +00:00
a2b8b60646
ARM load shifted register pre-index fix shift value asm parser encoding.
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llvm-svn: 137367
2011-08-11 22:05:09 +00:00
12d13efa21
Handle new register classes in Thumb2 mode. Should fix the ARM buildbots.
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llvm-svn: 137364
2011-08-11 21:52:38 +00:00
f05e744857
Making SEL decodings auto-generate-able.
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llvm-svn: 137363
2011-08-11 21:50:56 +00:00
88981ff168
Tidy up comment.
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llvm-svn: 137359
2011-08-11 21:41:59 +00:00
b685c9f011
Fix decoding support for STREXD and LDREXD.
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llvm-svn: 137356
2011-08-11 21:34:58 +00:00
d886f8cd8d
ARM STRH assembly parsing and encoding.
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llvm-svn: 137353
2011-08-11 21:17:22 +00:00
3a850f28d0
Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
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llvm-svn: 137347
2011-08-11 20:47:56 +00:00
2ea19d1438
Tidy up. Remove unused template parameter.
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llvm-svn: 137345
2011-08-11 20:41:13 +00:00
887c0b1358
Improve operand validation for Thumb2 addressing modes.
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llvm-svn: 137344
2011-08-11 20:40:40 +00:00
eb09f49a7f
ARM STRD assembly parsing and encoding.
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llvm-svn: 137342
2011-08-11 20:28:23 +00:00
6066340301
Continue to tighten decoding by performing more operand validation.
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llvm-svn: 137340
2011-08-11 20:21:46 +00:00
Nick Lewycky