Commit Graph

173485 Commits

Author SHA1 Message Date
Aaron Ballman 6c6fb80c2d Fix visualization of intrusive reference counted objects in MSVC.
llvm-svn: 350748
2019-01-09 18:59:56 +00:00
Thomas Lively edb54b22d3 [WebAssembly] Standardize order of SIMD bitselect arguments
Summary:
For some reason the backend assumed that the condition mask would be
the first argument to the LLVM intrinsic, but everywhere else the
condition mask is the third argument.

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D56412

llvm-svn: 350746
2019-01-09 18:13:11 +00:00
Sanjay Patel 15f2a4d1b9 [x86] use 'nounwind' to remove test noise; NFC
llvm-svn: 350745
2019-01-09 17:29:18 +00:00
Hubert Tong ea2ce500e9 [unittests][Support] AIX: Skip sticky bit file tests
On AIX, attempting (without root) to set the sticky bit on a file with
the `chmod` utility will give:
```
chmod: not all requested changes were made to <file>
```

The same occurs when modifying other permission bits on a file with the
sticky bit already set.

It seems that the `chmod` function will report success despite failing
to set the sticky bit.

llvm-svn: 350735
2019-01-09 16:00:39 +00:00
Aleksandar Beserminji 8abf680424 [mips][micrompis] Emit 16bit NOPs by default
Emit 16bit NOPs by default.
Use 32bit NOPs in delay slots where necessary.

Differential https://reviews.llvm.org/D55323

llvm-svn: 350733
2019-01-09 15:58:02 +00:00
Alexey Bataev 59e916c214 [DEBUGINFO][NVPTX]Make tests more strict, NFC.
NVPTX format requires that no labels/label arithmetics is used in the
debug info sections. To avoid possible problems with the adding/modifying the debug info functionality, made these tests more strict.

llvm-svn: 350731
2019-01-09 15:41:44 +00:00
Valery Pykhtin b7a459547d Revert "[AMDGPU] Fix DPP combiner"
This reverts commit e3e2923a39cbec3b3bc3a7d3f0e9a77a4115080e, svn revision rL350721

llvm-svn: 350730
2019-01-09 15:21:53 +00:00
Kristof Beyls c650ff77eb Initial AArch64 SLH implementation.
This is an initial implementation for Speculative Load Hardening for
AArch64. It builds on top of the recently introduced
AArch64SpeculationHardening pass.
This doesn't implement (yet) some of the optimizations implemented for
the X86SpeculativeLoadHardening pass. I thought introducing the
optimizations incrementally in follow-up patches should make this easier
to review.

Differential Revision: https://reviews.llvm.org/D55929

llvm-svn: 350729
2019-01-09 15:13:34 +00:00
George Rimar 3ba0f3c0fb [llvm-objdump] - Print symbol addressed when dumping disassembly output (-d)
When GNU objdump dumps the input with -d it prints the symbol addresses,
for example:

0000000000000031 <foo>:
  31:	00 00                	add    %al,(%rax)
	...

llvm-objdump currently does not do that.
Patch changes the behavior to match the GNU objdump.

That is useful for implementing -z/--disassemble-zeroes (D56083),
it allows omitting first zero bytes and keep the information
about the symbol address in the output.

Differential revision: https://reviews.llvm.org/D56123

llvm-svn: 350726
2019-01-09 14:43:33 +00:00
Nico Weber b61910bbe8 Fix typo in comment
llvm-svn: 350725
2019-01-09 14:20:20 +00:00
Simon Pilgrim fcabfc8666 [X86][SSE] Cleanup shuffle combining test check prefixes
Share prefixes whenever possible, use X86 instead of X32.

llvm-svn: 350722
2019-01-09 13:46:14 +00:00
Valery Pykhtin 1e0b5c719b [AMDGPU] Fix DPP combiner
Fixed issue with identity values and other cases, f32/f16 identity values to be added later. fma/mac instructions is disabled for now.
Test is fully reworked, added comments. Other fixes:

1. dpp move with uses and old reg initializer should be in the same BB.
2. bound_ctrl:0 is only considered when bank_mask and row_mask are fully enabled (0xF). Othervise the old register value is checked for identity.
3. Added add, subrev, and, or instructions to the old folding function.
4. Kill flag is cleared for the src0 (DPP register) as it may be copied into more than one user.

Differential revision: https://reviews.llvm.org/D55444

llvm-svn: 350721
2019-01-09 13:43:32 +00:00
Florian Hahn 9697d2a764 Revert r350647: "[NewPM] Port tsan"
This patch breaks thread sanitizer on some macOS builders, e.g.
http://green.lab.llvm.org/green/job/clang-stage1-configure-RA/52725/

llvm-svn: 350719
2019-01-09 13:32:16 +00:00
Simon Pilgrim 5a7132ff0f [X86] Enable combining shuffles to PACKSS/PACKUS for 256/512-bit vectors
llvm-svn: 350716
2019-01-09 13:23:28 +00:00
Anton Korobeynikov c18e90369d [MSP430] Optimize 'shl x, 8[+ N] -> swpb(zext(x)) [<< N]' for i16
Perform additional simplification to reduce shift amount.

Patch by Kristina Bessonova!

Differential Revision: https://reviews.llvm.org/D56016

llvm-svn: 350712
2019-01-09 13:03:01 +00:00
Nico Weber 2b0094b051 [gn build] Run `git ls-files '*.gn' '*.gni' | xargs -n 1 gn format`
Looks like I forgot to do that for the PowerPC target.

llvm-svn: 350711
2019-01-09 12:57:52 +00:00
Anton Korobeynikov 9222ed4485 [MSP430] Fix crash while lowering llvm.stacksave/stackrestore
Perform the usual expansion of stacksave / restore intrinsics.
Patch by Kristina Bessonova!

Differential Revision: https://reviews.llvm.org/D54890

llvm-svn: 350710
2019-01-09 12:52:15 +00:00
Nico Weber 7d497ea2d9 [gn build] Merge r350669
llvm-svn: 350709
2019-01-09 12:48:06 +00:00
Nico Weber 1faed50ab5 [gn build] Add a TODO.txt file
Differential Revision: https://reviews.llvm.org/D56420

llvm-svn: 350708
2019-01-09 12:46:04 +00:00
Simon Pilgrim 17eace47cb [X86] Add extra test coverage for combining shuffles to PACKSS/PACKUS
llvm-svn: 350707
2019-01-09 12:34:10 +00:00
Diogo N. Sampaio 1eb31c8e94 [AArch64] Move feature predctrl to predres
Follow up patch of rL350385, for adding predres
command line option. This patch renames the
feature as to keep it aligned with the option
passed by/to clang

Differential Revision: https://reviews.llvm.org/D56484

llvm-svn: 350702
2019-01-09 11:24:15 +00:00
Simon Pilgrim 7ee86e8e81 [X86] Fix gcc7 -Wunused-but-set-variable warning. NFCI.
llvm-svn: 350701
2019-01-09 11:18:49 +00:00
Alexander Kornienko af0d2a69c3 Make the write_cmake_config.py script python3-compatible
llvm-svn: 350700
2019-01-09 10:49:44 +00:00
David Stenberg 33b192d72b [DebugInfo] Omit location list entries with empty ranges
Summary:
This fixes PR39710. In that case we emitted a location list looking like
this:

.Ldebug_loc0:
        .quad   .Lfunc_begin0-.Lfunc_begin0
        .quad   .Lfunc_begin0-.Lfunc_begin0
        .short  1                       # Loc expr size
        .byte   85                      # DW_OP_reg5
        .quad   .Lfunc_begin0-.Lfunc_begin0
        .quad   .Lfunc_end0-.Lfunc_begin0
        .short  1                       # Loc expr size
        .byte   85                      # super-register DW_OP_reg5
        .quad   0
        .quad   0

As seen, the first entry's beginning and ending addresses evalute to 0,
which meant that the entry inadvertently became an "end of list" entry,
resulting in the location list ending sooner than expected.

To fix this, omit all entries with empty ranges. Location list entries
with empty ranges do not have any effect, as specified by DWARF, so we
might as well drop them:

"A location list entry (but not a base address selection or end of list
 entry) whose beginning and ending addresses are equal has no effect
 because the size of the range covered by such an entry is zero."

Reviewers: davide, aprantl, dblaikie

Reviewed By: aprantl

Subscribers: javed.absar, JDevlieghere, llvm-commits

Tags: #debug-info

Differential Revision: https://reviews.llvm.org/D55919

llvm-svn: 350698
2019-01-09 09:58:59 +00:00
Matt Arsenault 3dddb163dd GlobalISel: Implement fewerElements for implicit_def
llvm-svn: 350697
2019-01-09 07:51:52 +00:00
Matt Arsenault befee402ff GlobalISel: Implement widenScalar for implicit_def
llvm-svn: 350695
2019-01-09 07:34:14 +00:00
Max Kazantsev 4615a505f8 [IPT] Drop cache less eagerly in GVN and LoopSafetyInfo
Current strategy of dropping `InstructionPrecedenceTracking` cache is to
invalidate the entire basic block whenever we change its contents. In fact,
`InstructionPrecedenceTracking` has 2 internal strictures: `OrderedInstructions`
that is needed to be invalidated whenever the contents changes, and the map
with first special instructions in block. This second map does not need an
update if we add/remove a non-special instuction because it cannot
affect the contents of this map.

This patch changes API of `InstructionPrecedenceTracking` so that it now
accounts for reasons under which we invalidate blocks. This should lead
to much less recalculations of the map and should save us some compile time
because in practice we don't typically add/remove special instructions.

Differential Revision: https://reviews.llvm.org/D54462
Reviewed By: efriedma

llvm-svn: 350694
2019-01-09 07:28:13 +00:00
Zi Xuan Wu f2a75eef41 Revert "[PowerPC] Fix assert from machine verify pass that unmatched register class about fcmp selection in fast-isel"
This reverts commit r350685.

See compile assert in compiler-rt.

llvm-svn: 350693
2019-01-09 06:12:24 +00:00
Hiroshi Inoue dad8c6a1c9 [NFC] fix trivial typos in comments
llvm-svn: 350690
2019-01-09 05:11:10 +00:00
Peter Collingbourne 17f10abe1a gn build: Copy file permissions from input file in configure_file() emulation.
Most significantly, this makes bin/llvm-lit executable so that it
can be run in the usual way.

Differential Revision: https://reviews.llvm.org/D56423

llvm-svn: 350688
2019-01-09 04:39:29 +00:00
Craig Topper 2fa8e2d8a8 [X86] Correct the MaskVT for avx512 gather/scatter intrinsics to use the min of the number of index and data elements.
When the result type is v2i64/v2f64 and the index element size is i32, the index vector has two unused elements making the type v4i32. The mask VT should match the number of memory accesses that will be made.

This is consistent with the isel patterns used for the target independent gather/scatter intrinsic.

llvm-svn: 350687
2019-01-09 04:21:12 +00:00
Peter Collingbourne 634a143d48 gn build: Fix a Python2ism in write_vcsrevision.py.
Convert the output of "git rev-parse --short HEAD" to a string before
substituting it into the output file. Without this the output file
will look like this on Python 3:

 #define LLVM_REVISION "git-b'6a4895a025f'"

Differential Revision: https://reviews.llvm.org/D56459

llvm-svn: 350686
2019-01-09 04:05:07 +00:00
Zi Xuan Wu 9479f6d72e [PowerPC] Fix assert from machine verify pass that unmatched register class about fcmp selection in fast-isel
Bad machine code: Illegal virtual register for instruction

function: TestULE
basic block: %bb.0 entry (0x1000a39b158)
instruction: %2:crrc = FCMPUD %1:vsfrc, %3:f8rc
operand 1: %1:vsfrc

Fix assert about missing match between fcmp instruction and register class. 
We should use vsx related cmp instruction xvcmpudp instead of fcmpu when vsx is opened.

add -verifymachineinstrs option into related test cases to enable the verify pass.


Differential Revision: https://reviews.llvm.org/D55686

llvm-svn: 350685
2019-01-09 02:31:10 +00:00
Stanislav Mekhanoshin ed0d6c60af Remove check for single use in ShrinkDemandedConstant
This removes check for single use from general ShrinkDemandedConstant
to the BE because of the AArch64 regression after D56289/rL350475.

After several hours of experiments I did not come up with a testcase
failing on any other targets if check is not performed.

Moreover, direct call to ShrinkDemandedConstant is not really needed
and superceed by SimplifyDemandedBits.

Differential Revision: https://reviews.llvm.org/D56406

llvm-svn: 350684
2019-01-09 02:24:22 +00:00
Matt Arsenault 0ad1b71fe3 RegisterCoalescer: Assume CR_Replace for SubRangeJoin
Currently it's possible for following
check on V.WriteLanes (which is not really meaningful
during SubRangeJoin) to pass for one half of the pair,
and then fall through to to one of the impossible
or unresolved states. This then fails as inconsistent
on the other half.

During the main range join, the check between V.WriteLanes
and OtherV.ValidLanes must have passed, meaning this
should be a CR_Replace.

Fixes most of the testcases in bugs 39542 and 39602

llvm-svn: 350678
2019-01-08 23:22:18 +00:00
Matt Arsenault 2c807410fd RegisterCoalescer: Defer clearing implicit_def lanes
We can't go back and recover the lanes if it turns
out the implicit_def really can't be erased.

Assume all lanes are valid if an unresolved conflict
is encountered. There aren't any tests where this
seems to matter either way, but this seems like a
safer option.

Fixes bug 39602

llvm-svn: 350676
2019-01-08 23:10:47 +00:00
Sanjay Patel bad2406409 [InstCombine] remove stale comments; NFC
These changed with rL350672.

llvm-svn: 350674
2019-01-08 22:52:08 +00:00
Rong Xu 52aa224aff [llvm-profdata] add value-cutoff functionality in show command
This patch improves llvm-profdata show command:
(1) add -value-cutoff=<N> option: Show only those functions whose max count
    values are greater or equal to N.
(2) add -list-below-cutoff option: Only output names of functions whose max
    count value are below the cutoff.
(3) formats value-profile counts and prints out percentage.

Differential Revision: https://reviews.llvm.org/D56342

llvm-svn: 350673
2019-01-08 22:41:48 +00:00
Sanjay Patel d023dd60e9 [InstCombine] canonicalize another raw IR rotate pattern to funnel shift
This is matching the equivalent of the DAG expansion, 
so it should never end up with worse perf than the 
original code even if the target doesn't have a rotate
instruction.

llvm-svn: 350672
2019-01-08 22:39:55 +00:00
Rong Xu 016220549d [PGO] Use SourceFileName rather module name in PGOFuncName
In LTO or Thin-lto mode (though linker plugin), the module
names are of temp file names which are different for
different compilations. Using SourceFileName avoids the issue.
This should not change any functionality for current PGO as
all the current callers of getPGOFuncName() is before LTO.

Differential Revision: https://reviews.llvm.org/D56327

llvm-svn: 350671
2019-01-08 22:39:47 +00:00
Rong Xu 7162e16e6b [PGO] Revert r350579 to fix commit message.
Will re-commit it using the correct commit message.

llvm-svn: 350670
2019-01-08 22:37:12 +00:00
Heejin Ahn 321d522038 [WebAssembly] Rename StoreResults to MemIntrinsicResults
Summary:
StoreResults pass does not optimize store instructions anymore because
store instructions don't return results values anymore. Now this pass is
used solely for memory intrinsics, so update the pass name accordingly
and fix outdated pass descriptions as well.

This patch does not change any meaningful behavior, but not marked as
NFC because it changes a comment check line in a test case.

Reviewers: dschuff

Subscribers: mgorny, sbc100, jgravelle-google, sunfiish, llvm-commits

Differential Revision: https://reviews.llvm.org/D56093

llvm-svn: 350669
2019-01-08 22:35:18 +00:00
Rong Xu d236b0aa93 [PGO] Revert r350442 to fix commit message.
Will re-commit it using the correct commit message.

llvm-svn: 350667
2019-01-08 22:33:29 +00:00
Evandro Menezes 39c97bf6cd [AArch64] Adjust the cost model for Exynos
Improve the modeling of ALU instructions.

llvm-svn: 350663
2019-01-08 22:29:58 +00:00
Evandro Menezes 9b7b5b1dcc [llvm-mca] Update the Exynos test cases (NFC)
Add more entropy to the test cases.

llvm-svn: 350662
2019-01-08 22:29:56 +00:00
Evandro Menezes 5d780093fd [llvm-mca] Improve debugging (NFC)
llvm-svn: 350661
2019-01-08 22:29:38 +00:00
Jorge Gorbe Moya 4b284ef81a Fix go bindings for r350647: missed a function rename
Differential Revision: https://reviews.llvm.org/D56452

llvm-svn: 350657
2019-01-08 21:45:42 +00:00
Zachary Turner 2fe4900525 [llvm-undname] Add support for demangling msvc's noexcept types.
Starting in C++17, MSVC introduced a new mangling for function
parameters that are themselves noexcept functions.  This patch
makes llvm-undname properly demangle them.

Patch by Zachary Henkel
Differential Revision: https://reviews.llvm.org/D55769

llvm-svn: 350656
2019-01-08 21:05:51 +00:00
Zachary Turner 4e83923d83 Don't write #include "Windows/WindowsSupport.h" from the Windows dir.
This generates -Wnonportable-include-dir warnings, and doesn't need
to be there.  It seems this was just checked in on accident.

llvm-svn: 350655
2019-01-08 21:05:34 +00:00
Adrian Prantl 8a753a2e5a Revert "Revert "Revert "Resubmit rL345008 "Split MachinePipeliner code into header and cpp files""""
This reverts commit D56084.

llvm-svn: 350654
2019-01-08 21:05:10 +00:00