Commit Graph

5 Commits

Author SHA1 Message Date
Jia Liu b22310fda6 Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
llvm-svn: 150878
2012-02-18 12:03:15 +00:00
Jakob Stoklund Olesen b93331f3be Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.

This works well because TableGen resolves member references late:

class I : Instruction {
  AddrMode AM = AddrModeNone;
  let TSFlags{3-0} = AM.Value;
}

let AM = AddrMode4 in
def ADD : I;

TSFlags gets the expected bits from AddrMode4 in this example.

llvm-svn: 100384
2010-04-05 03:10:20 +00:00
Anton Korobeynikov 71471293a5 Provide instruction sizes & encoding. No opcodes yet (but not needed so far).
llvm-svn: 93553
2010-01-15 21:18:39 +00:00
Anton Korobeynikov e57b234b88 Add instruction formats & support stuff
llvm-svn: 93550
2010-01-15 21:17:13 +00:00
Anton Korobeynikov 101380015c Dummy MSP430 backend
llvm-svn: 70694
2009-05-03 12:57:15 +00:00