d6a39eaa70
Urg, right. These need an input value...
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llvm-svn: 11443
2004-02-14 04:47:23 +00:00
8bed37595d
add 'rep stos[bwd]' instructions
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llvm-svn: 11441
2004-02-14 04:45:37 +00:00
8dc99feeaf
Add support for the rep movs[bwd] instructions, and emit them when code
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generating the llvm.memcpy intrinsic.
llvm-svn: 11351
2004-02-12 17:53:22 +00:00
dbf4b42fde
IMULri* instructions do not require their first two registers operands
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to be the same (IOW they are not two address instructions).
llvm-svn: 11117
2004-02-04 17:21:04 +00:00
3c8c72c54f
Add the ftst instruction
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llvm-svn: 11095
2004-02-03 07:27:50 +00:00
63b61e8739
No need to declare implicit uses/defs of ST0
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llvm-svn: 11081
2004-02-02 19:57:45 +00:00
30d26ac561
Generate the fchs instruction to negate a floating point number
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llvm-svn: 11078
2004-02-02 19:31:38 +00:00
68cff6bf4d
Remove floating point killer pass. This is now implemented in the
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instruction selector by adding a new pseudo-instruction
FP_REG_KILL. This instruction implicitly defines all x86 fp registers
and is a terminator so that passes which add machine code at the end
of basic blocks (like phi elimination) do not add instructions between
it and the branch or return instruction.
llvm-svn: 10562
2003-12-20 16:22:59 +00:00
29265fe981
Added LLVM copyright header.
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llvm-svn: 9321
2003-10-21 15:17:13 +00:00
6acb1bedb1
Emit x86 instructions for: A = B op C, where A and B are 16-bit registers,
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C is a constant which can be sign-extended from 8 bits without value loss,
and op is one of: add, sub, imul, and, or, xor.
This allows the JIT to emit the one byte version of the constant instead of
the two or 4 byte version. Because these instructions are very common, this
can save a LOT of code space. For example, I sampled two benchmarks, 176.gcc
and 254.gap.
BM Old New Reduction
176.gcc 2673621 2548962 4.89%
254.gap 498261 475104 4.87%
Note that while the percentage is not spectacular, this did eliminate
124.6 _KILOBYTES_ of codespace from gcc. Not bad.
Note that this doesn't effect the llc version at all, because the assembler
already does this optimization.
llvm-svn: 9284
2003-10-20 05:53:31 +00:00
97e1b55723
* Rename X86::IMULr16 -> X86::IMULrr16
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* Implement R1 = R2 * C where R1 and R2 are 32 or 16 bits. This avoids an
extra copy into a register, reducing register pressure.
llvm-svn: 9278
2003-10-20 03:42:58 +00:00
55a8ef0cc8
Add some new instructions. Wheee
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llvm-svn: 9266
2003-10-19 19:25:35 +00:00
7235d86507
Add support for unconditional branches and for emitting JE instructions
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llvm-svn: 7872
2003-08-15 04:50:49 +00:00
7606fa0d41
Add basic support for 16 and 32 bit function arguments!
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llvm-svn: 7755
2003-08-11 21:30:00 +00:00
2923637f63
Add (ret int) expander so that we can at least write testcases
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llvm-svn: 7730
2003-08-11 15:48:00 +00:00
7fed97d00a
Add patterns for multiply, and, or, and xor
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llvm-svn: 7725
2003-08-11 15:23:25 +00:00
19d25b3c41
add a pattern for RET, immediates no longer need to be explicitly typed
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llvm-svn: 7635
2003-08-06 15:31:35 +00:00
7c257321c7
This is the real fix for the previous register allocator problem.
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Physical registers should not float around.
llvm-svn: 7587
2003-08-05 00:48:47 +00:00
148747e162
Add patterns for (mov R, R) (mov R, I) and subtracts. The moves are to enable
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testing, the subtracts are because I was in the neighborhood.
llvm-svn: 7581
2003-08-04 21:18:19 +00:00
44cdcf013f
Change comments into something that TableGen can read!
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llvm-svn: 7580
2003-08-04 21:08:29 +00:00
2551080937
transition to using let instead of set
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llvm-svn: 7564
2003-08-04 04:59:56 +00:00
59a4a91703
Add new TableGen instruction definitions
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llvm-svn: 7537
2003-08-03 21:54:21 +00:00
Chris Lattner