eb103c404b
Shorten up this testcase.
...
llvm-svn: 93187
2010-01-11 21:50:35 +00:00
7bdf339602
Revert 93158. It's breaking quite a few x86_64 tests.
...
llvm-svn: 93185
2010-01-11 21:13:41 +00:00
d2a1bee2d4
Avoid adding PHI arguments for a predecessor that has gone away when a BRCOND was constant folded.
...
This fixes PR5980.
llvm-svn: 93184
2010-01-11 21:02:33 +00:00
e99a3c191e
Use a 32-bit and with implicit zero-extension instead of a 64-bit and if it
...
has an immediate with at least 32 bits of leading zeros, to avoid needing to
materialize that immediate in a register first.
FileCheckize, tidy, and extend a testcase to cover this case.
This fixes rdar://7527390.
llvm-svn: 93160
2010-01-11 17:58:34 +00:00
3a55686345
Re-instate MOV64r0 and MOV16r0, with adjustments to work with the
...
new AsmPrinter. This is perhaps less elegant than describing them
in terms of MOV32r0 and subreg operations, but it allows the
current register to rematerialize them.
llvm-svn: 93158
2010-01-11 17:37:57 +00:00
31e8637ac2
Generalize this check to avoid depending on a specific register assignment.
...
llvm-svn: 93157
2010-01-11 17:24:27 +00:00
355ebc7f58
Make this test less trivial, to avoid spurious failures.
...
llvm-svn: 93156
2010-01-11 17:23:56 +00:00
64d9f40557
Select an OR with immediate as an ADD if the input bits are known zero. This allow the instruction to be 3address-fied if needed.
...
llvm-svn: 93152
2010-01-11 17:03:47 +00:00
206351a1ff
Implement a feature (-vector-unaligned-mem) to allow targets to
...
ignore alignment requirements for SIMD memory operands. This
is useful on architectures like the AMD 10h that do not trap on
unaligned references if a status bit is twiddled at startup time.
llvm-svn: 93151
2010-01-11 16:29:42 +00:00
bb857e5d68
Fix http://llvm.org/PR5729 : x86-64 tail calls were putting their targets into
...
R11, and then asserting that the target was in R9. Since R9 isn't reserved for
the target anymore, and is used as an argument, this patch changes the
assertion.
llvm-svn: 93065
2010-01-09 18:56:43 +00:00
6bd3ef82ff
Revert an earlier change to SIGN_EXTEND_INREG for vectors. The VTSDNode
...
really does need to be a vector type, because
TargetLowering::getOperationAction for SIGN_EXTEND_INREG uses that type,
and it needs to be able to distinguish between vectors and scalars.
Also, fix some more issues with legalization of vector casts.
llvm-svn: 93043
2010-01-09 02:13:55 +00:00
cc6d56bd3b
Fix a critical bug in 64-bit atomic operation lowering for 32-bit. The results of the cmpxchg8b instructions are being thrown away when it branches back to the top of the checking loop. This means the loop always compares against the old value and this can result in a dead lock.
...
llvm-svn: 93028
2010-01-08 23:41:50 +00:00
58ec4fec88
ReplaceAllUsesOfValueWith may delete other nodes that the one being replaced. Do not delete dead nodes again.
...
llvm-svn: 92988
2010-01-08 02:36:12 +00:00
dab2cd543f
Fix rdar://7517201, a regression introduced by r92849.
...
When folding a and(any_ext(load)) both the any_ext and the
load have to have only a single use.
This removes the anyext-uses.ll testcase which started failing
because it is unreduced and unclear what it is testing.
llvm-svn: 92950
2010-01-07 21:59:23 +00:00
16b75ce19c
APInt'fy TargetLowering::SimplifySetCC to fix PR5963.
...
llvm-svn: 92943
2010-01-07 20:58:44 +00:00
90dc43fcf5
Fix a minor regression from my dag combiner changes. One more place which needs to look pass truncates.
...
llvm-svn: 92885
2010-01-07 00:54:06 +00:00
f1522d612f
Add comments.
...
llvm-svn: 92883
2010-01-07 00:51:04 +00:00
29a64c9575
Add Target hook to duplicate machine instructions.
...
Some instructions refer to unique labels, and so cannot be trivially cloned
with CloneMachineInstr.
llvm-svn: 92873
2010-01-06 23:47:07 +00:00
166a4e6caa
Teach dag combine to fold the following transformation more aggressively:
...
(OP (trunc x), (trunc y)) -> (trunc (OP x, y))
Unfortunately this simple change causes dag combine to infinite looping. The problem is the shrink demanded ops optimization tend to canonicalize expressions in the opposite manner. That is badness. This patch disable those optimizations in dag combine but instead it is done as a late pass in sdisel.
This also exposes some deficiencies in dag combine and x86 setcc / brcond lowering. Teach them to look pass ISD::TRUNCATE in various places.
llvm-svn: 92849
2010-01-06 19:38:29 +00:00
f34b289057
Move this test from test/Transforms/IndVarSimplify to
...
test/CodeGen/X86, as doesn't use -indvars, and it does use
llc -march=x86-64.
llvm-svn: 92799
2010-01-05 22:52:54 +00:00
03f0af372c
Don't assign the shift the same type as the variable being shifted. This could
...
result in illegal types for the SHL operator.
llvm-svn: 92797
2010-01-05 22:39:10 +00:00
fb4193625a
Delete useless trailing semicolons.
...
llvm-svn: 92740
2010-01-05 17:55:26 +00:00
8c63ee7e28
Make this test more portable.
...
llvm-svn: 92514
2010-01-04 21:23:34 +00:00
52183c3cc9
Add some tests and update an existing test to reflect recent
...
x86 isel peeps.
llvm-svn: 92509
2010-01-04 20:53:54 +00:00
d91a14dba5
Fix invalid chain folding for memory variant of sdiv / udiv
...
llvm-svn: 92472
2010-01-04 10:31:54 +00:00
1dae8766b1
fix PR5930, allowing the asmprinter to emit difference between
...
two labels as a truncate.
llvm-svn: 92455
2010-01-03 18:33:18 +00:00
f6a585fc2f
add PR#
...
llvm-svn: 92451
2010-01-03 18:10:58 +00:00
a7cfc43af8
differences between two blockaddress's don't cause a
...
global variable initializer to require relocations.
llvm-svn: 92450
2010-01-03 18:09:40 +00:00
909c71c96a
allow this to work on linux hosts.
...
llvm-svn: 92407
2010-01-02 00:22:15 +00:00
1eea3b0ada
Teach codegen to handle:
...
(X != null) | (Y != null) --> (X|Y) != 0
(X == null) & (Y == null) --> (X|Y) == 0
so that instcombine can stop doing this for pointers. This is part of PR3351,
which is a case where instcombine doing this for pointers (inserting ptrtoint)
is pessimizing code.
llvm-svn: 92406
2010-01-02 00:00:03 +00:00
6eef072eb6
rename file.
...
llvm-svn: 92405
2010-01-01 23:55:04 +00:00
39f18e545e
Teach codegen to lower llvm.powi to an efficient (but not optimal)
...
multiply sequence when the power is a constant integer. Before, our
codegen for std::pow(.., int) always turned into a libcall, which was
really inefficient.
This should also make many gfortran programs happier I'd imagine.
llvm-svn: 92388
2010-01-01 03:32:16 +00:00
5967840a5f
Make this more likely to generate a libcall.
...
llvm-svn: 92387
2010-01-01 03:26:51 +00:00
015215ca86
Extern declaration for unordered.f32 libcall was not being emitted. Fixed that.
...
llvm-svn: 92242
2009-12-29 03:24:34 +00:00
1ecffe13b2
Fixed llc crash for zext (i1 -> i8) loads.
...
llvm-svn: 92201
2009-12-28 04:53:24 +00:00
f5e3ed64d5
handle equality memcmp of 8 bytes on x86-64 with two unaligned loads and a
...
compare. On other targets we end up with a call to memcmp because we don't
want 16 individual byte loads. We should be able to use movups as well, but
we're failing to select the generated icmp.
llvm-svn: 92107
2009-12-24 01:07:17 +00:00
1a32ede6fd
move an optimization for memcmp out of simplifylibcalls and into
...
SDISel. This optimization was causing simplifylibcalls to
introduce type-unsafe nastiness. This is the first step, I'll be
expanding the memcmp optimizations shortly, covering things that
we really really wouldn't want simplifylibcalls to do.
llvm-svn: 92098
2009-12-24 00:37:38 +00:00
cd419eebce
Reapply 91904.
...
llvm-svn: 91996
2009-12-23 11:19:09 +00:00
6920c17f1f
deleting empty file.
...
llvm-svn: 91994
2009-12-23 10:35:24 +00:00
f7b4f89588
Reverting back 91904.
...
llvm-svn: 91993
2009-12-23 09:46:01 +00:00
a864a67185
Use more sensible type for flags in asms. PR 5570.
...
Patch by Sylve`re Teissier (sorry, ASCII only).
llvm-svn: 91988
2009-12-23 07:32:51 +00:00
fdb33458fc
Update objectsize intrinsic and associated dependencies. Fix
...
lowering code and update testcases.
llvm-svn: 91979
2009-12-23 02:51:48 +00:00
ef3fdc1cbd
Add testcase for PR5703
...
llvm-svn: 91931
2009-12-22 22:37:23 +00:00
71d7eaa87e
Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size.
...
llvm-svn: 91910
2009-12-22 17:47:23 +00:00
8c5f05fcee
While converting one of the operands to a memory operand, we need to check if it is Legal and does not result into a cyclic dep.
...
llvm-svn: 91904
2009-12-22 14:25:37 +00:00
8ac077df57
Emit direction operand in binary insns that stores in memory.
...
llvm-svn: 91777
2009-12-19 13:52:01 +00:00
bda8002e7f
Test cases for changes done in 91768.
...
llvm-svn: 91773
2009-12-19 11:38:14 +00:00
b175de6356
Increase opportunities to optimize (brcond (srl (and c1), c2)).
...
llvm-svn: 91717
2009-12-18 21:31:31 +00:00
4cf30b72bf
On recent Intel u-arch's, folding loads into some unary SSE instructions can
...
be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.
movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0
instead of
cvtss2sd (%rdi), %xmm0
An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0
llvm-svn: 91672
2009-12-18 07:40:29 +00:00
51fbfb726f
Tidy up this testcase and add test for tailcall optimization
...
with unreachable.
llvm-svn: 91650
2009-12-18 01:05:06 +00:00
3152b0471b
Handle ARM inline asm "w" constraints with 64-bit ("d") registers.
...
The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types. Radar 7457110.
llvm-svn: 91649
2009-12-18 01:03:29 +00:00
7f4326f8b6
Remove "tail" keywords. These calls are not intended to be tail calls.
...
This protects this test from depending on codegen not performing the
tail call optimization by default.
llvm-svn: 91648
2009-12-18 01:02:18 +00:00
78c5919b14
Add test case for the phi reuse patch.
...
llvm-svn: 91642
2009-12-18 00:11:44 +00:00
04d8cb74f3
Instruction fixes, added instructions, and AsmString changes in the
...
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
llvm-svn: 91638
2009-12-18 00:01:26 +00:00
aadf060b92
Revert this dag combine change:
...
Fold (zext (and x, cst)) -> (and (zext x), cst)
DAG combiner likes to optimize expression in the other way so this would end up cause an infinite looping.
llvm-svn: 91574
2009-12-17 00:40:05 +00:00
23fbd54cfe
Make this test pass on Linux.
...
llvm-svn: 91521
2009-12-16 07:35:25 +00:00
1be6286028
Re-enable 91381 with fixes.
...
llvm-svn: 91489
2009-12-16 00:53:11 +00:00
56f041406d
Do better with physical reg operands (typically, from inline asm)
...
in local register allocator. If a reg-reg copy has a phys reg
input and a virt reg output, and this is the last use of the phys
reg, assign the phys reg to the virt reg. If a reg-reg copy has
a phys reg output and we need to reload its spilled input, reload
it directly into the phys reg than passing it through another reg.
Following 76208, there is sometimes no dependency between the def of
a phys reg and its use; this creates a window where that phys reg
can be used for spilling (this is true in linear scan also). This
is bad and needs to be fixed a better way, although 76208 works too
well in practice to be reverted. However, there should normally be
no spilling within inline asm blocks. The patch here goes a long way
towards making this actually be true.
llvm-svn: 91485
2009-12-16 00:29:41 +00:00
792f0913ee
For fastcc on x86, let ECX be used as a return register after EAX and EDX
...
llvm-svn: 91410
2009-12-15 03:27:52 +00:00
fcb5453dc7
Disable 91381 for now. It's miscompiling ARMISelDAG2DAG.cpp.
...
llvm-svn: 91405
2009-12-15 03:07:11 +00:00
852c486946
Make 91378 more conservative.
...
1. Only perform (zext (shl (zext x), y)) -> (shl (zext x), y) when y is a constant. This makes sure it remove at least one zest.
2. If the shift is a left shift, make sure the original shift cannot shift out bits.
llvm-svn: 91399
2009-12-15 03:00:32 +00:00
0e8b9e32d1
Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's.
...
llvm-svn: 91381
2009-12-15 00:53:42 +00:00
d1521ef40c
Fold (zext (and x, cst)) -> (and (zext x), cst).
...
llvm-svn: 91380
2009-12-15 00:52:11 +00:00
ca7c690d3b
Propagate zest through logical shift.
...
llvm-svn: 91378
2009-12-15 00:41:36 +00:00
cecad35728
Fix integer cast code to handle vector types.
...
llvm-svn: 91362
2009-12-14 23:40:38 +00:00
26fdd7265b
Disable r91104 for x86. It causes partial register stall which pessimize code in 32-bit.
...
llvm-svn: 91223
2009-12-12 20:03:14 +00:00
e27e028cdd
Lower setcc branchless, if this is profitable.
...
Based on the patch by Brian Lucas!
llvm-svn: 91175
2009-12-11 23:01:29 +00:00
1d459e4937
Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG.
...
llvm-svn: 91158
2009-12-11 21:31:27 +00:00
bffa061e02
Change this to the correct PR number.
...
llvm-svn: 91148
2009-12-11 20:09:21 +00:00
6d306bb32b
Fix the result type of SELECT nodes lowered from Select instructions with
...
aggregate return values. This fixes PR5754.
llvm-svn: 91145
2009-12-11 19:50:50 +00:00
fc51282cbe
Honour setHasCalls() set from isel.
...
This is used in some weird cases like general dynamic TLS model.
This fixes PR5723
llvm-svn: 91144
2009-12-11 19:39:55 +00:00
ff2ac71b25
Tests for 91103 and 91104.
...
llvm-svn: 91105
2009-12-11 06:02:21 +00:00
4986588ddb
It's not safe to coalesce a move where src and dst registers have different subregister indices. e.g.:
...
%reg16404:1<def> = MOV8rr %reg16412:2<kill>
llvm-svn: 91061
2009-12-10 20:59:45 +00:00
2262909b20
Fix test.
...
llvm-svn: 90988
2009-12-09 22:24:42 +00:00
493b882f80
Optimize splat of a scalar load into a shuffle of a vector load when it's legal. e.g.
...
vector_shuffle (scalar_to_vector (i32 load (ptr + 4))), undef, <0, 0, 0, 0>
=>
vector_shuffle (v4i32 load ptr), undef, <1, 1, 1, 1>
iff ptr is 16-byte aligned (or can be made into 16-byte aligned).
llvm-svn: 90984
2009-12-09 21:00:30 +00:00
d938faff4b
Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 isl lowering code.
...
llvm-svn: 90925
2009-12-09 01:53:58 +00:00
0c2544fd6b
- Support inline asm 'w' constraint for 128-bit vector types.
...
- Also support the 'q' NEON registers asm code.
llvm-svn: 90894
2009-12-08 23:06:22 +00:00
dd2b2f8cba
Reduce (cmp 0, and_su (foo, bar)) into (bit foo, bar). This saves extra instruction. Patch inspired by Brian Lucas!
...
llvm-svn: 90819
2009-12-08 01:03:04 +00:00
76a7edc36d
Use FileCheck and set nounwind on calls.
...
llvm-svn: 90790
2009-12-07 19:40:26 +00:00
9528ccdd77
Don't enable the post-RA scheduler on x86 except at -O3. In its
...
current form, it is too expensive in compile time.
llvm-svn: 90781
2009-12-07 19:04:31 +00:00
75dfed4fa5
Dynamic stack realignment use of sp register as source/dest register
...
in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode.
Emit the following code instead:
mov r4, sp
bic r4, r4, #15
mov sp, r4
llvm-svn: 90724
2009-12-06 22:39:50 +00:00
f89986235d
Temporarily revert r90502. It was causing the llvm-gcc bootstrap on PPC to fail.
...
llvm-svn: 90653
2009-12-05 07:30:23 +00:00
ca9cf65455
Also attempt trivial coalescing for live intervals that end in a copy.
...
The coalescer is supposed to clean these up, but when setting up parameters
for a function call, there may be copies to physregs. If the defining
instruction has been LICM'ed far away, the coalescer won't touch it.
The register allocation hint does not always work - when the register
allocator is backtracking, it clears the hints.
This patch takes care of a few more cases that r90163 missed.
llvm-svn: 90502
2009-12-04 00:16:04 +00:00
9655f84662
Don't pull vector sext through both hands of a logical operation, since doing so prevents the fusion of vector sext and setcc into vsetcc.
...
Add a testcase for the above transformation.
Fix a bogus use of APInt noticed while tracking this down.
llvm-svn: 90423
2009-12-03 07:11:29 +00:00
0bbd3077ce
Recognize canonical forms of vector shuffles where the same vector is used for
...
both source operands. In the canonical form, the 2nd operand is changed to an
undef and the shuffle mask is adjusted to only reference elements from the 1st
operand. Radar 7434842.
llvm-svn: 90417
2009-12-03 06:40:55 +00:00
76bf386af0
Remove unnecessary check.
...
llvm-svn: 90352
2009-12-02 22:02:20 +00:00
732351f732
Fix PR5391: support early clobber physical register def tied with a use (ewwww)
...
- A valno should be set HasRedefByEC if there is an early clobber def in the middle of its live ranges. It should not be set if the def of the valno is defined by an early clobber.
- If a physical register def is tied to an use and it's an early clobber, it just means the HasRedefByEC is set since it's still one continuous live range.
- Add a couple of missing checks for HasRedefByEC in the coalescer. In general, it should not coalesce a vr with a physical register if the physical register has a early clobber def somewhere. This is overly conservative but that's the price for using such a nasty inline asm "feature".
llvm-svn: 90269
2009-12-01 22:25:00 +00:00
8a8ba87ac8
test case for IV-Users simplification loop improvement
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llvm-svn: 90260
2009-12-01 21:53:51 +00:00
26667abbd3
Use CFG connectedness as a secondary sort key when deciding the order of copy coalescing.
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This means that well connected blocks are copy coalesced before the less connected blocks. Connected blocks are more difficult to
coalesce because intervals are more complicated, so handling them first gives a greater chance of success.
llvm-svn: 90194
2009-12-01 03:03:00 +00:00
1d31fc9123
Fix PR5614: parts of a physical register def may be killed the rest.
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llvm-svn: 90180
2009-12-01 00:44:45 +00:00
020d8d4c63
New virtual registers created for spill intervals should inherit allocation hints from the original register.
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This helps us avoid silly copies when rematting values that are copied to a physical register:
leaq _.str44(%rip), %rcx
movq %rcx, %rsi
call _strcmp
becomes:
leaq _.str44(%rip), %rsi
call _strcmp
The coalescer will not touch the movq because that would tie down the physical register.
llvm-svn: 90163
2009-11-30 22:55:54 +00:00
031cb00246
Add test case for r90108
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llvm-svn: 90109
2009-11-30 02:42:27 +00:00
b56334b4f2
While this test is testing a problem in the generic part of codegen,
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the problem only shows for msp430 and pic16 which is why it specifies
them using -march. But it is wrong to put such tests in CodeGen/Generic,
since not everyone builds these targets. Put a copy of the test in each
of the target test directories.
llvm-svn: 90005
2009-11-27 16:04:14 +00:00
a4c986cbdd
Test for 89905.
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llvm-svn: 89906
2009-11-26 00:35:01 +00:00
44df27e964
ProcessImplicitDefs should watch out for invalidated iterator and extra implicit operands on copies.
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llvm-svn: 89880
2009-11-25 21:13:39 +00:00
2db07581b7
Support PIC loading of constant pool entries
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llvm-svn: 89863
2009-11-25 12:17:58 +00:00
5ece8f0a20
Do not store R31 into the caller's link area on PPC.
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This violates the ABI (that area is "reserved"), and
while it is safe if all code is generated with current
compilers, there is some very old code around that uses
that slot for something else, and breaks if it is stored
into. Adjust testcases looking for current behavior.
I've verified that the stack frame size is right in all
testcases, whether it changed or not. 7311323.
llvm-svn: 89811
2009-11-24 22:59:02 +00:00
184ec26fcd
Enable predication of NEON instructions in Thumb2 mode.
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llvm-svn: 89748
2009-11-24 08:06:15 +00:00
2522908653
Materialize global addresses via movt/movw pair, this is always better
...
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.
This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).
llvm-svn: 89720
2009-11-24 00:44:37 +00:00
dbb4140f37
move fconst[sd] to UAL. <rdar://7414913>
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llvm-svn: 89700
2009-11-23 21:08:25 +00:00
50b293d65e
update test for 89694
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llvm-svn: 89695
2009-11-23 20:39:53 +00:00
f161e97a9e
Miss two, PR5307.
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llvm-svn: 89596
2009-11-22 15:35:28 +00:00
cc856372b0
Convert Thumb2 tests to FileCheck for PR5307.
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llvm-svn: 89595
2009-11-22 15:18:27 +00:00
a9268a4525
Turns out stuff gets allocated to different registers depending on the subtarget.
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llvm-svn: 89594
2009-11-22 15:15:52 +00:00
21d7e8aeb1
Convert ARM tests to FileCheck for PR5307.
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llvm-svn: 89593
2009-11-22 14:23:33 +00:00
2e245f4e18
Convert test to FileCheck.
...
llvm-svn: 89589
2009-11-22 13:16:36 +00:00
8966897524
Forgot to alter RUN line when converting to FileCheck.
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llvm-svn: 89588
2009-11-22 13:09:48 +00:00
7150767800
Fix for bad FileCheck converts in revision 89584.
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llvm-svn: 89586
2009-11-22 12:50:05 +00:00
15dd46215e
Convert a few tests to FileCheck for PR5307.
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llvm-svn: 89584
2009-11-22 11:45:44 +00:00
e09e95b35c
Revert 89562. We're being sneakier than I was giving us credit for, and this
...
isn't necessary.
llvm-svn: 89568
2009-11-21 23:34:09 +00:00
43fd822249
Darwin requires a frame pointer for all non-leaf functions to support correct
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backtraces.
llvm-svn: 89562
2009-11-21 21:40:08 +00:00
4c83e2c253
Don't leave temporary files in the test directory.
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llvm-svn: 89531
2009-11-21 02:05:31 +00:00
b91eba382d
When generating a vector the really slow way, via loads
...
and stores, handle the case where the element size is not
a valid target type correctly (PPC).
llvm-svn: 89521
2009-11-21 00:53:23 +00:00
73f9a9e2c8
Enable hoisting load from constant memories.
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llvm-svn: 89510
2009-11-20 23:31:34 +00:00
c1f532e930
Recommitting PALIGNR shift width fixes.
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Thanks to Daniel Dunbar for fixing clang intrinsics:
http://llvm.org/viewvc/llvm-project?view=rev&revision=89499
llvm-svn: 89500
2009-11-20 22:28:42 +00:00
8495a506eb
Remove an incorrect overaggressive optimization
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(PPC specific).
llvm-svn: 89496
2009-11-20 22:16:40 +00:00
19d92728d0
Reverting PALIGNR fix until I figure out how this
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broke the Clang testsuite.
llvm-svn: 89495
2009-11-20 22:09:28 +00:00
fbed130173
Fixed PALIGNR to take 8-bit rotations in all cases.
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Also fixed the corresponding testcase, and the PALIGNR
intrinsic (tested for correctness with llvm-gcc).
llvm-svn: 89491
2009-11-20 21:40:28 +00:00
bdb43a9d99
Remat VLDRD from constpool. Clean up some instruction property specifications.
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llvm-svn: 89478
2009-11-20 19:57:15 +00:00
cc0a0cb4b7
Fix PR5558, which was caused by a wrong fix for PR3393 (see commit 63048),
...
which was an expensive checks failure due to a bug in the checking. This
patch in essence reverts the original fix for PR3393, and refixes it by a
tweak to the way expensive checking is done.
llvm-svn: 89454
2009-11-20 10:45:10 +00:00
20c8ab655e
Fix fast-isel to avoid selecting the return instruction if a
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tail call has been encountered.
llvm-svn: 89444
2009-11-20 02:51:26 +00:00
bbd50b0f78
Also CSE non-pic load from constant pools.
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llvm-svn: 89440
2009-11-20 02:10:27 +00:00
81a2851bcb
Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all.
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llvm-svn: 89423
2009-11-20 00:54:03 +00:00
0b2099ad5f
Unbreak test, Bruno please check.
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llvm-svn: 89329
2009-11-19 07:18:49 +00:00
b18525937c
More consistent thumb1 asm printing.
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llvm-svn: 89328
2009-11-19 06:57:41 +00:00
2a6c92fcb6
Shrink ldr / str [sp, imm0-1024] to 16-bit instructions.
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llvm-svn: 89326
2009-11-19 06:32:27 +00:00
4713b282ce
- Add sugregister logic to handle f64=(f32,f32).
...
- Support mips1 like load/store of doubles:
Instead of:
sdc $f0, X($3)
Generate:
swc $f0, X($3)
swc $f1, X+4($3)
llvm-svn: 89322
2009-11-19 06:06:13 +00:00
77f0ea6b93
Test from Dhrystone to make sure that we're not emitting an aligned load for a
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string that's aligned at 8-bytes instead of 16-bytes.
llvm-svn: 89295
2009-11-19 01:33:57 +00:00
6456fb94f5
Fix buildbots.
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llvm-svn: 89274
2009-11-18 23:30:38 +00:00
3bd09434a6
Add XCore support for indirectbr / blockaddress.
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llvm-svn: 89273
2009-11-18 23:20:42 +00:00
108aadf972
Tail duplication still needs to iterate. Duplicating new instructions onto
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the tail of a block may make that block a new candidate for duplication.
llvm-svn: 89264
2009-11-18 22:52:37 +00:00
575c3f3d72
Fix PR5300.
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When TwoAddressInstructionPass deletes a dead instruction, make sure that all
register kills are accounted for. The 2-addr register does not get special
treatment.
llvm-svn: 89246
2009-11-18 21:33:35 +00:00
4797e58d6b
Fix inverted test and add testcase from failing self-host.
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llvm-svn: 89167
2009-11-18 00:02:18 +00:00
50ee5e7ddb
Remove fragile test.
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llvm-svn: 89150
2009-11-17 21:52:40 +00:00
cdde77c6a3
Enable arm jumpt table adjustment.
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llvm-svn: 89143
2009-11-17 21:24:11 +00:00
a2873f4d59
Forgot to commit test fixes
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llvm-svn: 89138
2009-11-17 20:38:36 +00:00
fffff88a3c
Enable -split-phi-edges by default, except when -regalloc=local.
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The local register allocator doesn't like it when LiveVariables is run.
We should also disable edge splitting under -O0, but that has to wait a bit.
llvm-svn: 89125
2009-11-17 19:15:50 +00:00
84efacfaad
Revert 89021. It's miscompiling llvm-gcc driver driver at -O0.
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llvm-svn: 89082
2009-11-17 09:55:52 +00:00
9f0d55d8d8
Enable -split-phi-edges by default
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llvm-svn: 89021
2009-11-17 01:07:22 +00:00
d33400e636
MOV64rm should be marked isReMaterializable.
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llvm-svn: 89019
2009-11-17 00:55:55 +00:00
0ad7efbace
Convert to FileCheck
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llvm-svn: 89007
2009-11-17 00:20:26 +00:00
4781c3caf8
Convert to FileCheck
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llvm-svn: 89002
2009-11-17 00:03:38 +00:00
805d195649
Cleanup. Missed removing these when converting. Oops.
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llvm-svn: 89001
2009-11-17 00:00:33 +00:00
b43e1ff236
Fix this test - there don't appear to be any actual Reload Reuses
...
in this testcase.
llvm-svn: 88998
2009-11-16 23:49:55 +00:00
9dede3b383
Revert r87049, which was the workaround for the regression triggered
...
by the recent FixedStackPseudoSourceValue-related changes, now that
the specific bug that affected it is fixed, in r88954.
llvm-svn: 88997
2009-11-16 23:43:42 +00:00
1deb0b9f53
Convert to FileCheck
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llvm-svn: 88991
2009-11-16 23:19:29 +00:00
f25ef4ffb0
- Check memoperand alignment instead of checking stack alignment. Most load / store folding instructions are not referencing spill stack slots.
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- Mark MOVUPSrm re-materializable.
llvm-svn: 88974
2009-11-16 21:56:03 +00:00
9b32e22ad1
Convert to FileCheck
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llvm-svn: 88947
2009-11-16 20:04:15 +00:00
16f6b3e607
Added a testcase for PR5495.
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llvm-svn: 88946
2009-11-16 20:03:13 +00:00
980d94164d
Convert to FileCheck
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llvm-svn: 88942
2009-11-16 19:46:46 +00:00
David Greene