5638c36efd
Handle AddrMode6 (for NEON load/stores) in Thumb2's rewriteT2FrameIndex.
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Radar 7614112.
llvm-svn: 95456
2010-02-06 00:24:38 +00:00
045f81981a
Revert LoopStrengthReduce.cpp to pre-r94061 for now.
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llvm-svn: 94123
2010-01-22 00:46:49 +00:00
51ad99d2c5
Re-implement the main strength-reduction portion of LoopStrengthReduction.
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This new version is much more aggressive about doing "full" reduction in
cases where it reduces register pressure, and also more aggressive about
rewriting induction variables to count down (or up) to zero when doing so
reduces register pressure.
It currently uses fairly simplistic algorithms for finding reuse
opportunities, but it introduces a new framework allows it to combine
multiple strategies at once to form hybrid solutions, instead of doing
all full-reduction or all base+index.
llvm-svn: 94061
2010-01-21 02:09:26 +00:00
bdc17f6840
Remove predicates when changing an add into an unpredicable mov.
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Since the mov is executed unconditionally, make sure that the add didn't have
any predicate.
llvm-svn: 93909
2010-01-19 21:08:28 +00:00
298cdac99c
Run the pre-register allocation tail duplication pass by default. Remove
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the -pre-regalloc-taildup command-line option, and add a new
-disable-early-taildup option.
llvm-svn: 93597
2010-01-16 00:29:50 +00:00
f1522d612f
Add comments.
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llvm-svn: 92883
2010-01-07 00:51:04 +00:00
29a64c9575
Add Target hook to duplicate machine instructions.
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Some instructions refer to unique labels, and so cannot be trivially cloned
with CloneMachineInstr.
llvm-svn: 92873
2010-01-06 23:47:07 +00:00
fb4193625a
Delete useless trailing semicolons.
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llvm-svn: 92740
2010-01-05 17:55:26 +00:00
23fbd54cfe
Make this test pass on Linux.
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llvm-svn: 91521
2009-12-16 07:35:25 +00:00
75dfed4fa5
Dynamic stack realignment use of sp register as source/dest register
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in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode.
Emit the following code instead:
mov r4, sp
bic r4, r4, #15
mov sp, r4
llvm-svn: 90724
2009-12-06 22:39:50 +00:00
8a8ba87ac8
test case for IV-Users simplification loop improvement
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llvm-svn: 90260
2009-12-01 21:53:51 +00:00
184ec26fcd
Enable predication of NEON instructions in Thumb2 mode.
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llvm-svn: 89748
2009-11-24 08:06:15 +00:00
dbb4140f37
move fconst[sd] to UAL. <rdar://7414913>
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llvm-svn: 89700
2009-11-23 21:08:25 +00:00
50b293d65e
update test for 89694
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llvm-svn: 89695
2009-11-23 20:39:53 +00:00
f161e97a9e
Miss two, PR5307.
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llvm-svn: 89596
2009-11-22 15:35:28 +00:00
cc856372b0
Convert Thumb2 tests to FileCheck for PR5307.
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llvm-svn: 89595
2009-11-22 15:18:27 +00:00
e09e95b35c
Revert 89562. We're being sneakier than I was giving us credit for, and this
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isn't necessary.
llvm-svn: 89568
2009-11-21 23:34:09 +00:00
43fd822249
Darwin requires a frame pointer for all non-leaf functions to support correct
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backtraces.
llvm-svn: 89562
2009-11-21 21:40:08 +00:00
73f9a9e2c8
Enable hoisting load from constant memories.
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llvm-svn: 89510
2009-11-20 23:31:34 +00:00
bdb43a9d99
Remat VLDRD from constpool. Clean up some instruction property specifications.
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llvm-svn: 89478
2009-11-20 19:57:15 +00:00
bbd50b0f78
Also CSE non-pic load from constant pools.
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llvm-svn: 89440
2009-11-20 02:10:27 +00:00
b18525937c
More consistent thumb1 asm printing.
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llvm-svn: 89328
2009-11-19 06:57:41 +00:00
2a6c92fcb6
Shrink ldr / str [sp, imm0-1024] to 16-bit instructions.
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llvm-svn: 89326
2009-11-19 06:32:27 +00:00
cdde77c6a3
Enable arm jumpt table adjustment.
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llvm-svn: 89143
2009-11-17 21:24:11 +00:00
a2873f4d59
Forgot to commit test fixes
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llvm-svn: 89138
2009-11-17 20:38:36 +00:00
0ad7efbace
Convert to FileCheck
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llvm-svn: 89007
2009-11-17 00:20:26 +00:00
4781c3caf8
Convert to FileCheck
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llvm-svn: 89002
2009-11-17 00:03:38 +00:00
805d195649
Cleanup. Missed removing these when converting. Oops.
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llvm-svn: 89001
2009-11-17 00:00:33 +00:00
1deb0b9f53
Convert to FileCheck
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llvm-svn: 88991
2009-11-16 23:19:29 +00:00
9b32e22ad1
Convert to FileCheck
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llvm-svn: 88947
2009-11-16 20:04:15 +00:00
980d94164d
Convert to FileCheck
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llvm-svn: 88942
2009-11-16 19:46:46 +00:00
c670bdc311
tbb opt off by default
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llvm-svn: 88921
2009-11-16 17:24:45 +00:00
01c1cae34d
Detect need for autoalignment of the stack earlier to catch spills more
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conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling
llvm-svn: 88874
2009-11-15 21:45:34 +00:00
f16a3b7a9f
remove xfail
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llvm-svn: 88817
2009-11-14 21:57:35 +00:00
66401c90da
When expanding t2STRDi8 r, r to two stores, add kill markers correctly.
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llvm-svn: 88734
2009-11-14 01:50:00 +00:00
1025a4998b
Clean up testcase a bit. Simplify case blocks and adjust switch instruction to not take an undefined value as input.
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llvm-svn: 86997
2009-11-12 17:19:09 +00:00
5218176bc6
Fix typo in run line.
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llvm-svn: 86984
2009-11-12 12:35:27 +00:00
5d85a46f76
RegScavenger::enterBasicBlock should always reset register state.
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llvm-svn: 86972
2009-11-12 07:49:10 +00:00
85a9f430e9
- Teach LSR to avoid changing cmp iv stride if it will create an immediate that
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cannot be folded into target cmp instruction.
- Avoid a phase ordering issue where early cmp optimization would prevent the
later count-to-zero optimization.
- Add missing checks which could cause LSR to reuse stride that does not have
users.
- Fix a bug in count-to-zero optimization code which failed to find the pre-inc
iv's phi node.
- Remove, tighten, loosen some incorrect checks disable valid transformations.
- Quite a bit of code clean up.
llvm-svn: 86969
2009-11-12 07:35:05 +00:00
64b5d0f468
Add support for tail duplication to BranchFolding, and extend
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tail merging support to handle more cases.
- Recognize several cases where tail merging is beneficial even when
the tail size is smaller than the generic threshold.
- Make use of MachineInstrDesc::isBarrier to help detect
non-fallthrough blocks.
- Check for and avoid disrupting fall-through edges in more cases.
llvm-svn: 86871
2009-11-11 19:48:59 +00:00
47e3bcf180
Update test
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llvm-svn: 86614
2009-11-09 22:59:01 +00:00
d7cf55cd0e
Use Unified Assembly Syntax for the ARM backend.
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llvm-svn: 86494
2009-11-09 00:11:35 +00:00
a8e8a7c976
Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic.
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llvm-svn: 86330
2009-11-07 04:04:34 +00:00
7ff831962a
- Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical
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except it doesn't care if the definitions' virtual registers differ. This is
used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
Since pc relative constantpool entries are always different, this requires it
it check if the values can actually the same.
llvm-svn: 86328
2009-11-07 03:52:02 +00:00
207b246650
- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
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load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.
llvm-svn: 86304
2009-11-06 23:52:48 +00:00
db42ca663b
Fix a broken test.
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llvm-svn: 86298
2009-11-06 23:06:42 +00:00
8f4e3d99c9
Fix test.
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llvm-svn: 85986
2009-11-04 00:42:33 +00:00
8d681f0471
Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8.
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llvm-svn: 85871
2009-11-03 05:52:54 +00:00
2c2dc9f64f
Temporary xfail until PR5367 will be resolved
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llvm-svn: 85848
2009-11-03 00:37:36 +00:00
1708b06c0e
Unbreak ARMBaseRegisterInfo::copyRegToReg.
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llvm-svn: 85787
2009-11-02 04:44:55 +00:00
Bob Wilson