a570d05228
tighten up eh.setjmp sequence a bit.
...
llvm-svn: 95603
2010-02-08 23:22:00 +00:00
d9d7186dc0
unify the paths for external symbols and global variables:
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2 files changed, 48 insertions(+), 83 deletions(-)
llvm-svn: 95599
2010-02-08 23:03:41 +00:00
99777dd78f
switch the rest of the "@ concatentation" logic in the X86
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backend to use X86MCTargetExpr, simplifying a bunch of code.
llvm-svn: 95595
2010-02-08 22:52:47 +00:00
4d16049c61
Fixed the AT&T AsmLexer to report the proper strings
...
for register tokens. Before, if it encountered
'%al,' it would report 'al,' as the token. Now it
correctly reports '%al'.
llvm-svn: 95594
2010-02-08 22:50:23 +00:00
b8479fb309
switch ELF @GOTOFF references to use X86MCTargetExpr.
...
llvm-svn: 95593
2010-02-08 22:33:55 +00:00
b6b2164e28
add an x86 implementation of MCTargetExpr for
...
representing @GOT and friends. Use it for
personality references as a first use.
llvm-svn: 95588
2010-02-08 22:09:08 +00:00
9e60686a83
Add VCVTR (between floating-point and integer, VFP) for disassembly purpose.
...
The 'R' suffix means the to-integer operations use the rounding mode specified
by the FPSCR, encoded as Inst{7} = 0.
A8.6.295
llvm-svn: 95584
2010-02-08 22:02:41 +00:00
3464a5b609
Rename the PerformTailCallOpt variable to GuaranteedTailCallOpt to reflect
...
its current purpose.
llvm-svn: 95564
2010-02-08 20:27:50 +00:00
beb1238a85
Add VCMP (VFP floating-point compare without 'E' bit set) for disassembly purpose.
...
llvm-svn: 95560
2010-02-08 19:41:48 +00:00
c7e606f132
Added VMOVRRS/VMOVSRR to ARMInstrVFP.td for disassembly purpose.
...
A8.6.331 VMOV (between two ARM core registers and two single-precision registers)
llvm-svn: 95548
2010-02-08 17:26:09 +00:00
6e29e9d262
Fix x86 JIT stub on MSVC.
...
Thanks to Kristaps Straupe for noticing the bug.
llvm-svn: 95537
2010-02-08 08:37:27 +00:00
d59cddc098
Add suport for VASTART on Mips.
...
llvm-svn: 95506
2010-02-06 21:00:02 +00:00
d6fff557db
First step towards varargs support in Mips:
...
- o32 cc must pass all arguments in A0...A3 and stack regardless
if its type (but respect the alignment).
- Store all variable arguments back to the caller stack.
llvm-svn: 95500
2010-02-06 19:20:49 +00:00
ea5c6be766
Run codegen dce pass for all targets at all optimization levels. Previously it's
...
only run for x86 with fastisel. I've found it being very effective in
eliminating some obvious dead code as result of formal parameter lowering
especially when tail call optimization eliminated the need for some of the loads
from fixed frame objects. It also shrinks a number of the tests. A couple of
tests no longer make sense and are now eliminated.
llvm-svn: 95493
2010-02-06 09:07:11 +00:00
4536b9a904
Fix alignment on ppc linux. This fixes the build of crtend.o
...
llvm-svn: 95477
2010-02-06 03:32:21 +00:00
d064aefefc
Do not emit callseq instructions around sibcalls. This eliminated some unnecessary stack adjustments.
...
llvm-svn: 95475
2010-02-06 03:28:46 +00:00
74bb06c0f0
Reintroduce the InlineHint function attribute.
...
This time it's for real! I am going to hook this up in the frontends as well.
The inliner has some experimental heuristics for dealing with the inline hint.
When given a -respect-inlinehint option, functions marked with the inline
keyword are given a threshold just above the default for -O3.
We need some experiments to determine if that is the right thing to do.
llvm-svn: 95466
2010-02-06 01:16:28 +00:00
5638c36efd
Handle AddrMode6 (for NEON load/stores) in Thumb2's rewriteT2FrameIndex.
...
Radar 7614112.
llvm-svn: 95456
2010-02-06 00:24:38 +00:00
9d624778a3
fix incorrect encoding of SBB8mi that Kevin noticed.
...
llvm-svn: 95448
2010-02-05 22:56:11 +00:00
d91f302a05
fix a case where we'd mis-encode fisttp because of an incorrect (and
...
redundant with a correct one) pattern that was added for the disassembler.
llvm-svn: 95446
2010-02-05 22:49:06 +00:00
a60af09414
add note.
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llvm-svn: 95445
2010-02-05 22:48:33 +00:00
58827ff98e
port X86InstrInfo::determineREX over to the new encoder.
...
llvm-svn: 95440
2010-02-05 22:10:22 +00:00
9c9453e582
wire up 64-bit MCCodeEmitter.
...
llvm-svn: 95438
2010-02-05 21:51:35 +00:00
86bd194234
really kill off the last MRMInitReg inst, remove logic from encoder.
...
llvm-svn: 95437
2010-02-05 21:34:18 +00:00
e96d534ce0
lower the last of the MRMInitReg instructions in MCInstLower.
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llvm-svn: 95435
2010-02-05 21:30:49 +00:00
90916287ed
teach X86MCInstLower to lower the MOV32r0 and MOV8r0
...
pseudo instructions.
llvm-svn: 95433
2010-02-05 21:21:06 +00:00
fd7976a432
genericize helpers, use them for MOV16r0/MOV64r0
...
llvm-svn: 95432
2010-02-05 21:15:57 +00:00
340b542f8b
factor code better in X86MCInstLower::Lower, teach it to
...
lower the SETB* instructions.
llvm-svn: 95431
2010-02-05 21:13:48 +00:00
89f7dfff21
implement the rest of the encoding types.
...
llvm-svn: 95414
2010-02-05 19:37:31 +00:00
503243559a
move functions for decoding X86II values into the X86II namespace.
...
llvm-svn: 95410
2010-02-05 19:24:13 +00:00
342762fdba
constant propagate a method away.
...
llvm-svn: 95408
2010-02-05 19:20:30 +00:00
b8d375fd21
change getSizeOfImm and getBaseOpcodeFor to just take
...
TSFlags directly instead of a TargetInstrDesc.
llvm-svn: 95405
2010-02-05 19:16:26 +00:00
37166eb419
add some more encodings.
...
llvm-svn: 95403
2010-02-05 19:04:37 +00:00
a778db9a91
VMOVRRD and VMOVDRR both have Inst{7-6} = 0b00.
...
llvm-svn: 95397
2010-02-05 18:04:58 +00:00
df84b1aa50
implement the non-relocation forms of memory operands
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llvm-svn: 95368
2010-02-05 06:16:07 +00:00
a366c61f77
Handle tail call with byval arguments.
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llvm-svn: 95351
2010-02-05 02:21:12 +00:00
610c84a7c2
start adding MRMDestMem, which requires memory form mod/rm encoding
...
to start limping.
llvm-svn: 95350
2010-02-05 02:18:40 +00:00
4f627ba89f
Add a few more encodings, we can now encode all of:
...
pushl %ebp
movl %esp, %ebp
movl $42, %eax
popl %ebp
ret
llvm-svn: 95344
2010-02-05 01:53:19 +00:00
ee9d33b4e7
Disable external stubs for X86-32 and X86-64
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Instruction selection for X86 now can choose an instruction
sequence that will fit any address of any symbol, no matter
the pointer width. X86-64 uses a mov+call-via-reg sequence
for this.
llvm-svn: 95323
2010-02-04 19:56:59 +00:00
fb5670fc16
move the PR6214 microoptzn to this file.
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llvm-svn: 95299
2010-02-04 07:32:01 +00:00
aeba2250a5
Re-enable x86 tail call optimization.
...
llvm-svn: 95295
2010-02-04 06:47:24 +00:00
8228b11abc
add support for the sparcv9-*-* target triple to turn on
...
64-bit sparc codegen. Patch by Nathan Keynes!
llvm-svn: 95293
2010-02-04 06:34:01 +00:00
9976832a05
Indirect tail call has to go through a call preserved register since it's after callee register pops. X86 isel lowering is using EAX / R11 and it was somehow adding that to function live out. That prevented the real function return register from being added to the function live out list and bad things happen.
...
This fixes 483.xalancbmk (with tail call opt).
llvm-svn: 95280
2010-02-04 02:40:39 +00:00
c337d6538a
Rewrite FP constant handling in DEBUG_VALUE yet
...
again, so it more or less handles long double.
Restore \n removed in latest MC frenzy.
llvm-svn: 95271
2010-02-04 01:33:43 +00:00
223084d3ac
enhance new encoder to support prefixes + RawFrm
...
instructions with no operands. It can now handle
define void @test2() nounwind { ret void }
llvm-svn: 95261
2010-02-03 21:57:59 +00:00
6794f9b9f6
set up some infrastructure, some minor cleanups.
...
llvm-svn: 95260
2010-02-03 21:43:43 +00:00
f4139067ee
Speculatively disable x86 automatic tail call optimization while we track down a self-hosting issue.
...
llvm-svn: 95259
2010-02-03 21:40:40 +00:00
f914be06d2
stub out a new X86 encoder, which can be tried with
...
-enable-new-x86-encoder until its stable.
llvm-svn: 95256
2010-02-03 21:24:49 +00:00
2f750f3b5a
rename createX86MCCodeEmitter to more accurately reflect what it creates.
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llvm-svn: 95254
2010-02-03 21:14:33 +00:00
00f1e6c030
Added support for X86 instruction prefixes so llvm-mc can assemble them. The
...
Lock prefix, Repeat string operation prefixes and the Segment override prefixes.
Also added versions of the move string and store string instructions without the
repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of
move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is
happy building the disassembler files.
llvm-svn: 95252
2010-02-03 21:04:42 +00:00
Jim Grosbach