Commit Graph

139286 Commits

Author SHA1 Message Date
Daniel Jasper 90d990e034 Revert "[libFuzzer] refactoring to speed things up, NFC"
This reverts commit r283946.

This breaks when build with GCC:
lib/Fuzzer/FuzzerTracePC.cpp:169:6: error: always_inline function might not be inlinable [-Werror=attributes]
lib/Fuzzer/FuzzerTracePC.cpp:169:6: error: inlining failed in call to always_inline 'void fuzzer::TracePC::HandleCmp(void*, T, T) [with T = long unsigned int]': target specific option mismatch
lib/Fuzzer/FuzzerTracePC.cpp:198:65: error: called from here

llvm-svn: 283979
2016-10-12 07:26:46 +00:00
Quentin Colombet a907b5ca7c [AArch64][InstructionSelector] Fix unintended test changes in r283973.
I screwed up my merge conflict and lost some of the CHECK lines.

llvm-svn: 283974
2016-10-12 04:12:44 +00:00
Quentin Colombet 9de30faeac [AArch64][InstrustionSelector] Teach the selector about G_BITCAST.
llvm-svn: 283973
2016-10-12 03:57:52 +00:00
Quentin Colombet cb629a897c [AArch64][InstructionSelector] Refactor the handling of copies.
Although Copies are not specific to preISel, we still have to assign them
a proper register class. However, given they are not constrained to
anything we do not have to handle the source register at the copy. It
will be properly mapped when reaching the related definition.

In the process, the handlong of G_ANYEXT is slightly modified as those
end up being selected as copy. The difference is that when register size
do not match on both sides, we need to insert SUBREG_TO_REG operation,
otherwise the post RA copy expansion will not be happy!

llvm-svn: 283972
2016-10-12 03:57:49 +00:00
Quentin Colombet 5a0f5d4831 [AArch64][InstructionSelector] Fix typos in the related mir file. NFC.
llvm-svn: 283971
2016-10-12 03:57:46 +00:00
Quentin Colombet 404e4350dc [AArch64][MachineLegalizer] Mark more bitcasts as legal.
Those are copies, we do not have to do any legalization action for them.

llvm-svn: 283970
2016-10-12 03:57:43 +00:00
Brian Gesiak 8d89c3c6f7 [lit] Run unit tests as part of lit test suite
Summary:
The Python file `utils/lit/lit/ShUtil.py` contains:

1. Logic used by lit itself
2. A set of unit tests for that logic, which can be run by invoking
  `python utils/lit/lit/ShUtil.py`

Move these unit tests to a `tests/unit` subdirectory of lit, and run
the tests as part of lit's test suite. This ensures that, should the
lit test suite be included in LLVM's own regression test suite, these
unit tests will also be run.

(Instructions on how to run lit's test suite can be found in
`utils/lit/README.txt`.)

Reviewers: ddunbar, echristo, delcypher, beanz

Subscribers: mehdi_amini, llvm-commits

Differential Revision: https://reviews.llvm.org/D25411

llvm-svn: 283968
2016-10-12 03:35:04 +00:00
Sebastian Pop d57d93c9de Memory-SSA cleanup of clobbers interface, NFC
This implements the cleanup that Danny asked to commit separately from the
previous fix to GVN-hoist in https://reviews.llvm.org/D25476#inline-219818

Tested with ninja check on x86_64-linux.

llvm-svn: 283967
2016-10-12 03:08:40 +00:00
Sebastian Pop ab12fb62ee GVN-hoist: fix store past load dependence analysis (PR30216, PR30499)
This is a refreshed version of a patch that was reverted: it fixes
the problems reported in both PR30216 and PR30499, and
contains all the test-cases from both bugs.

To hoist stores past loads, we used to search for potential
conflicting loads on the hoisting path by following a MemorySSA
def-def link from the store to be hoisted to the previous
defining memory access, and from there we followed the def-use
chains to all the uses that occur on the hoisting path. The
problem is that the def-def link may point to a store that does
not alias with the store to be hoisted, and so the loads that are
walked may not alias with the store to be hoisted, and even as in
the testcase of PR30216, the loads that may alias with the store
to be hoisted are not visited.

The current patch visits all loads on the path from the store to
be hoisted to the hoisting position and uses the alias analysis
to ask whether the store may alias the load. I was not able to
use the MemorySSA functionality to ask for whether load and
store are clobbered: I'm not sure which function to call, so I
used a call to AA->isNoAlias().

Store past store is still working as before using a MemorySSA
query: I added an extra test to pr30216.ll to make sure store
past store does not regress.

Tested on x86_64-linux with check and a test-suite run.

Differential Revision: https://reviews.llvm.org/D25476

llvm-svn: 283965
2016-10-12 02:23:39 +00:00
Tim Shen 4ff62b187e [PPCMIPeephole] Fix splat elimination
Summary:
In PPCMIPeephole, when we see two splat instructions, we can't simply do the following transformation:
  B = Splat A
  C = Splat B
=>
  C = Splat A
because B may still be used between these two instructions. Instead, we should make the second Splat a PPC::COPY and let later passes decide whether to remove it or not:
  B = Splat A
  C = Splat B
=>
  B = Splat A
  C = COPY B

Fixes PR30663.

Reviewers: echristo, iteratee, kbarton, nemanjai

Subscribers: mehdi_amini, llvm-commits

Differential Revision: https://reviews.llvm.org/D25493

llvm-svn: 283961
2016-10-12 00:48:25 +00:00
Reid Kleckner 038febb3e4 Fix the stage2 MSVC 2013 build with less constexpr in RNG
llvm-svn: 283954
2016-10-11 23:02:21 +00:00
Michael Kuperstein 7adbf6b042 [DAG] Fix crash in build_vector -> vector_shuffle combine
Fixes a crash in the build_vector -> vector_shuffle combine
when the first vector input is twice as wide as the output,
and the second input vector is even wider.

llvm-svn: 283953
2016-10-11 22:44:31 +00:00
Tim Northover c1d8c2bf8c GlobalISel: support same-size casts on AArch64.
Mostly Ahmed's work again, I'm just sprucing things up slightly before
committing.

llvm-svn: 283952
2016-10-11 22:29:23 +00:00
Vedant Kumar de2ae96710 [InstrProf] Add support for dead_strip+live_support functionality
On Darwin, marking a section as "regular,live_support" means that a
symbol in the section should only be kept live if it has a reference to
something that is live. Otherwise, the linker is free to dead-strip it.

Turn this functionality on for the __llvm_prf_data section.

This means that counters and data associated with dead functions will be
removed from dead-stripped binaries. This will result in smaller
profiles and binaries, and should speed up profile collection.

Tested with check-profile, llvm-lit test/tools/llvm-{cov,profdata}, and
check-llvm.

Differential Revision: https://reviews.llvm.org/D25456

llvm-svn: 283947
2016-10-11 21:48:16 +00:00
Kostya Serebryany a09d11e108 [libFuzzer] refactoring to speed things up, NFC
llvm-svn: 283946
2016-10-11 21:27:37 +00:00
Reid Kleckner bdfc05ff93 Re-land "[Thumb] Save/restore high registers in Thumb1 pro/epilogues"
Reverts r283938 to reinstate r283867 with a fix.

The original change had an ArrayRef referring to a destroyed temporary
initializer list. Use plain C arrays instead.

llvm-svn: 283942
2016-10-11 21:14:03 +00:00
Kevin Enderby 68fffa8a62 Next set of additional error checks for invalid Mach-O files for the
load commands that uses the MachO::linker_option_command
type but not used in llvm libObject code but used in llvm tool code.

This includes just LC_LINKER_OPTION load command.

llvm-svn: 283939
2016-10-11 21:04:39 +00:00
Reid Kleckner f4876beb2b Revert "[Thumb] Save/restore high registers in Thumb1 pro/epilogues"
This reverts r283867.

This appears to be an infinite loop:

    while (HiRegToSave != AllHighRegs.end() && CopyReg != AllCopyRegs.end()) {
      if (HiRegsToSave.count(*HiRegToSave)) {
        ...

        CopyReg = findNextOrderedReg(++CopyReg, CopyRegs, AllCopyRegs.end());
        HiRegToSave =
            findNextOrderedReg(++HiRegToSave, HiRegsToSave, AllHighRegs.end());
      }
    }

llvm-svn: 283938
2016-10-11 20:54:41 +00:00
Tim Northover 3d38b3a4d1 GlobalISel: support selection of extend operations.
Patch mostly by Ahmed Bougaca.

llvm-svn: 283937
2016-10-11 20:50:21 +00:00
Tim Northover 60cf6fc58f MIRParser: allow types on registers with a RegBank.
This fixes some GlobalISel regression tests.

llvm-svn: 283936
2016-10-11 20:50:04 +00:00
Jordan Rose 764f9f7806 Re-apply "Disallow ArrayRef assignment from temporaries."
This re-applies r283798, disabled in r283803, with the static_assert
tests disabled under MSVC. The deleted functions still seem to catch
mistakes in MSVC, so it's not a significant loss.

Part of rdar://problem/16375365

llvm-svn: 283935
2016-10-11 20:39:16 +00:00
Kyle Butt 0846e56e63 Codegen: Tail-duplicate during placement.
The tail duplication pass uses an assumed layout when making duplication
decisions. This is fine, but passes up duplication opportunities that
may arise when blocks are outlined. Because we want the updated CFG to
affect subsequent placement decisions, this change must occur during
placement.

In order to achieve this goal, TailDuplicationPass is split into a
utility class, TailDuplicator, and the pass itself. The pass delegates
nearly everything to the TailDuplicator object, except for looping over
the blocks in a function. This allows the same code to be used for tail
duplication in both places.

This change, in concert with outlining optional branches, allows
triangle shaped code to perform much better, esepecially when the
taken/untaken branches are correlated, as it creates a second spine when
the tests are small enough.

Issue from previous rollback fixed, and a new test was added for that
case as well. Issue was worklist/scheduling/taildup issue in layout.

Issue from 2nd rollback fixed, with 2 additional tests. Issue was
tail merging/loop info/tail-duplication causing issue with loops that share
a header block.

Issue with early tail-duplication of blocks that branch to a fallthrough
predecessor fixed with test case: tail-dup-branch-to-fallthrough.ll

Differential revision: https://reviews.llvm.org/D18226

llvm-svn: 283934
2016-10-11 20:36:43 +00:00
Sanjay Patel c2bd185dc4 [x86] add tests for negate bool
llvm-svn: 283930
2016-10-11 20:15:20 +00:00
Reid Kleckner 5d0bc63d91 Avoid braced initialization for default member initializers for MSVC 2013
llvm-svn: 283928
2016-10-11 20:02:57 +00:00
Arnold Schwaighofer 9103e268cf Silence -Wunused-but-set-variable warning
llvm-svn: 283927
2016-10-11 19:49:29 +00:00
Rui Ueyama f9904043ca Re-submit r283823: Define DbiStreamBuilder::addDbgStream to add stream.
The previous commit was failing because we filled empty slots of
the debug stream index with kInvalidStreamIndex. It should've been 0.

llvm-svn: 283925
2016-10-11 19:43:12 +00:00
Kostya Serebryany 4d25ad93f3 [sanitizer-coverage] use private linkage for coverage guards, delete old commented-out code.
llvm-svn: 283924
2016-10-11 19:36:50 +00:00
Rui Ueyama 888de9b031 Fix build error on LP64 platforms.
llvm-svn: 283922
2016-10-11 19:28:56 +00:00
Zachary Turner 733be51dcd [raw_ostream] Raise some helper functions out of raw_ostream.
Low level functionality to format numbers were embedded in the
implementation of raw_ostream.  I have need to use these through
an interface other than the overloaded stream operators, so they
need to be raised to a level that they can be used from either
raw_ostream operators or other code.

llvm-svn: 283921
2016-10-11 19:24:45 +00:00
Konstantin Zhuravlyov cdd4547607 [AMDGPU] Refactor waitcnt encoding
- Refactor bit packing/unpacking
- Calculate bit mask given bit shift and bit width
- Introduce function for decoding bits of waitcnt
- Introduce function for encoding bits of waitcnt
- Introduce function for getting waitcnt mask (instead of using bare numbers)
- Introduce function fot getting max waitcnt(s) (instead of using bare numbers)

Differential Revision: https://reviews.llvm.org/D25298

llvm-svn: 283919
2016-10-11 18:58:22 +00:00
Dehao Chen e9d075233a Allow Switch instruction to have extractProfTotalWeight called as it can terminate a basic block. (NFC)
llvm-svn: 283918
2016-10-11 18:53:00 +00:00
Reid Kleckner a012dac9d6 Avoid unnecessary constexpr to appease MSVC 2013
llvm-svn: 283916
2016-10-11 18:35:13 +00:00
Mehdi Amini caec5559cb Fix "static initialization order fiasco" for the XCore Target.
I fixed all the other Targets in r283702, and interestingly the
sanitizers are only now "sometimes" catching this bug on the only
one I missed.

llvm-svn: 283914
2016-10-11 18:22:41 +00:00
Zachary Turner 76e007e7e3 [Support] Fix undefined behavior in RandomNumberGenerator.
This has existed pretty much forever AFAICT, but the code was
never being exercised because nobody was using the class.  A
user of this class surfaced, and now we're breaking with UB.
The code was obviously wrong, so it's fixed here.

llvm-svn: 283912
2016-10-11 18:17:26 +00:00
Konstantin Zhuravlyov 78f3fa774b [AMDGPU] Fix test that was broken by rL283893
llvm-svn: 283911
2016-10-11 18:16:56 +00:00
NAKAMURA Takumi e9587bd771 ARMMachineFunctionInfo.cpp: Add an initializer of ARMFunctionInfo::ReturnRegsCount in the explicit ctor.
It caused crash since r283867.

llvm-svn: 283909
2016-10-11 17:38:30 +00:00
NAKAMURA Takumi e61de02016 Reformat.
llvm-svn: 283908
2016-10-11 17:38:25 +00:00
Sanjay Patel 8253e15ef3 [DAG] add fold for masked negated sign-extended bool
This enhances the fold added with:
https://reviews.llvm.org/rL283900

llvm-svn: 283905
2016-10-11 17:05:52 +00:00
Sanjay Patel 58b4987284 [x86] add sext variants of tests added with r283894
llvm-svn: 283903
2016-10-11 16:49:52 +00:00
Bernard Ogden c5164132fe Let test pass for builds that support X86, but do not default to it
Differential Revision: https://reviews.llvm.org/D25471

llvm-svn: 283902
2016-10-11 16:34:49 +00:00
Bernard Ogden 2cf7ca3f35 Fix test on non-x86 hosts
Summary:
This test is allowed to run on non-x86 hosts and thus must use
llvm-nm rather than nm.

Differential Revision: https://reviews.llvm.org/D25473

llvm-svn: 283901
2016-10-11 16:32:37 +00:00
Sanjay Patel 8384703d9b [DAG] add fold for masked negated extended bool
The non-obvious motivation for adding this fold (which already happens in InstCombine)
is that we want to canonicalize IR towards select instructions and canonicalize DAG 
nodes towards boolean math. So we need to recreate some folds in the DAG to handle that
change in direction. 

An interesting implementation difference for cases like this is that InstCombine
generally works top-down while the DAG goes bottom-up. That means we need to detect 
different patterns. In this case, the SimplifyDemandedBits fold prevents us from 
performing a zext to sext fold that would then be recognized as a negation of a sext. 

llvm-svn: 283900
2016-10-11 16:26:36 +00:00
Daniel Jasper b617286089 Silence unused warning in non-assert builds.
llvm-svn: 283899
2016-10-11 16:22:36 +00:00
Adam Nemet 3996caa1a6 [opt-viewer] Remove unnecessary call to demangle
llvm-svn: 283898
2016-10-11 16:20:40 +00:00
Adam Nemet e437504b30 [opt-viewer] Print hotness as percentage of the maximum hotness
llvm-svn: 283897
2016-10-11 16:20:38 +00:00
Adam Nemet 4415e96aec [opt-viewer] Convert another HTML output to use a multiline string
llvm-svn: 283896
2016-10-11 16:19:06 +00:00
Sanjay Patel 9b3c8a7321 [x86] add tests to show missed folds for masked bools
llvm-svn: 283894
2016-10-11 16:04:37 +00:00
Changpeng Fang 98317d20f4 AMDGPU/SI: Update ISA version numbers for Tonga and Polaris10/11.
Differential Revision:
  http://reviews.llvm.org/D25454

Reviewers:
  tstellarAMD

llvm-svn: 283893
2016-10-11 16:00:47 +00:00
Zachary Turner 79f3333d3f [cl] Don't print subcommand help when no subcommands present.
Previously we would print

  USAGE: <exe> [subcommand] [options]

Even if no subcommands were present.  This changes the output
format to only print "[subcommand]" if there is at least one
subcommand.

Fixes llvm.org/pr30598

Patch by Serge Guelton

llvm-svn: 283892
2016-10-11 15:58:48 +00:00
Sanjay Patel 38a42e4bfa [DAG] simplify logic; NFC
llvm-svn: 283885
2016-10-11 14:14:30 +00:00