maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
99,982 Commits 23 Branches 0 Tags 2.2 GiB
Commit Graph

208 Commits

Author SHA1 Message Date
Evan Cheng bb8420a070 Fix PLD encoding. 
llvm-svn: 124458
 2011-01-27 23:48:34 +00:00
Bruno Cardoso Lopes ce0af9c961 Add encoding testcases for ARM vcvtr variations 
llvm-svn: 124289
 2011-01-26 13:53:38 +00:00
Bruno Cardoso Lopes 178c1e0c9b fix the encoding and add testcases for ARM nop, yield, wfe and wfi instructions 
llvm-svn: 124288
 2011-01-26 13:28:14 +00:00
Bruno Cardoso Lopes 4bd612384a Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm", 
qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This
is described in ARM manuals and matches the encoding used by the gnu assembler.

llvm-svn: 123975
 2011-01-21 14:07:40 +00:00
Bruno Cardoso Lopes 1f69de3983 Add testcases for clz encoding 
llvm-svn: 123937
 2011-01-20 19:27:16 +00:00
Bruno Cardoso Lopes e965f06f7f Fix the encoding and parsing of clrex instruction 
llvm-svn: 123936
 2011-01-20 19:18:32 +00:00
Bruno Cardoso Lopes d8f9b37f31 Add cdp/cdp2 instructions for thumb/thumb2 
llvm-svn: 123929
 2011-01-20 18:32:09 +00:00
Bruno Cardoso Lopes 33461ecc82 - Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present 
in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions.
- Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t
hem.

llvm-svn: 123927
 2011-01-20 18:06:58 +00:00
Bruno Cardoso Lopes 4d4b490fb7 Add mcr*2 and mr*c2 support to thumb2 targets 
llvm-svn: 123919
 2011-01-20 16:58:48 +00:00
Bruno Cardoso Lopes cf99dc7eb9 Add mcr* and mr*c support to thumb targets 
llvm-svn: 123917
 2011-01-20 16:35:57 +00:00
Bruno Cardoso Lopes d6335ce508 Fix the encoding of mrrc and mcrr family of instructions. Also add testcases for mcr and mrc 
llvm-svn: 123837
 2011-01-19 16:56:52 +00:00
Owen Anderson dac7a0174e When matching asm operands, always try to match the most restricted type first. 
Unfortunately, while this is the "right" thing to do, it breaks some ARM
asm parsing tests because MemMode5 and ThumbMemModeReg are ambiguous.  This
is tricky to resolve since neither is a subset of the other.

XFAIL the test for now.  The old way was broken in other ways, just ways
we didn't happen to be testing, and our ARM asm parsing is going to require
significant revisiting at a later point anyways.

llvm-svn: 123786
 2011-01-18 23:01:21 +00:00
Bruno Cardoso Lopes 2082057b18 Create two new generic classes to represent the following VMRS/VMSR variations: 
vmrs  reg, fpexc
vmrs  reg, fpsid
vmsr  fpexc, reg
vmsr  fpsid, reg

llvm-svn: 123783
 2011-01-18 21:58:20 +00:00
Bruno Cardoso Lopes cba727f291 Fix MRS encoding for arm and thumb. 
llvm-svn: 123778
 2011-01-18 21:31:35 +00:00
Bruno Cardoso Lopes e86a7ad01a Fix the encoding of t2ISB by using the right class and also parse it correctly 
llvm-svn: 123776
 2011-01-18 21:17:09 +00:00
Bruno Cardoso Lopes e6290ccf9b Follow the current hack set and enable the correct parsing of bkpt while in thumb mode. 
llvm-svn: 123772
 2011-01-18 20:55:11 +00:00
Bruno Cardoso Lopes 7f639c11d7 Add support for parsing and encoding ARM's official syntax for the BFI instruction 
llvm-svn: 123770
 2011-01-18 20:45:56 +00:00
Daniel Dunbar 66e91d4a58 McARM: Start marking T2 address operands as such, for the benefit of the parser. 
llvm-svn: 123722
 2011-01-18 03:06:03 +00:00
Evan Cheng d4a5c05c97 Completed :lower16: / :upper16: support for movw / movt pairs on Darwin. 
- Fixed :upper16: fix up routine. It should be shifting down the top 16 bits first.
- Added support for Thumb2 :lower16: and :upper16: fix up.
- Added :upper16: and :lower16: relocation support to mach-o object writer.

llvm-svn: 123424
 2011-01-14 02:38:49 +00:00
Evan Cheng 965b3c7323 Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step 
in the right direction. It eliminated some hacks and will unblock codegen
work. But it's far from being done. It doesn't reject illegal expressions,
e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all.

llvm-svn: 123369
 2011-01-13 07:58:56 +00:00
Bill Wendling e6ff05c59d Sort the register list based on the *actual* register numbers rather than the 
enum values we give to them. <rdar://problem/8823730>

llvm-svn: 123321
 2011-01-12 21:20:59 +00:00
Jason W Kim 9c5b65d289 1. Support ELF pcrel relocations for movw/movt: 
R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC.
2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum.
3. Add support for 3 new elf section types (no-ops)

llvm-svn: 123294
 2011-01-12 00:19:25 +00:00
Jason W Kim 1f7bc0707d Workaround for bug 8721. 
.s Test added.

llvm-svn: 123292
 2011-01-11 23:53:41 +00:00
Daniel Dunbar 9d944b3fcc McARM: Add more hard coded logic to SplitMnemonicAndCC to also split out the 
carry setting flag from the mnemonic.

Note that this currently involves me disabling a number of working cases in
arm_instructions.s, this is a hopefully short term evil which will be rapidly
fixed (and greatly surpassed), assuming my current approach flies.

llvm-svn: 123238
 2011-01-11 15:59:50 +00:00
Daniel Dunbar c0e8756ba9 McARM: Flush out hard coded known non-predicated mnemonic list. 
llvm-svn: 123189
 2011-01-10 21:01:03 +00:00
Bob Wilson fa27a8621c Add Neon VCVT instructions for f32 <-> f16 conversions. 
Clang is now providing intrinsics for these and so we need to support them
in the backend.  Radar 8068427.

llvm-svn: 121902
 2010-12-15 22:14:12 +00:00
Bob Wilson c3ff538dcf Fix misspelled target triples in MC/ARM test commands. 
llvm-svn: 121901
 2010-12-15 22:14:01 +00:00
Kevin Enderby 4886cc8be7 Add some more MC tests for ARM arithmetic instructions that update or don't 
update the condition codes.  These come from my test generator and are just
the ones that MC currently assembles correctly.

llvm-svn: 121830
 2010-12-15 01:24:36 +00:00
Daniel Dunbar a9b9300bb8 MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup. 
llvm-svn: 121772
 2010-12-14 17:37:16 +00:00
Kevin Enderby 3164a346e6 Add support for parsing ARM arithmetic instructions that update or don't update 
the condition codes.  Where the ones that do have an 's' suffix and the ones
that don't don't have the suffix.  The trick is if MatchInstructionImpl() fails
we try again after adding a CCOut operand with the correct value and removing
the 's' if present.  Four simple test cases added for now, lots more to come.

llvm-svn: 121401
 2010-12-09 19:19:43 +00:00
Jim Grosbach 567ebd0cb5 Encode the 32-bit wide Thumb (and Thumb2) instructions with the high order 
halfword being emitted to the stream first. rdar://8728174

llvm-svn: 120848
 2010-12-03 22:31:40 +00:00
Owen Anderson 6187e66801 Add tests for more forms of Thumb2 loads and stores. 
llvm-svn: 120436
 2010-11-30 18:15:21 +00:00
Bill Wendling 811c936ed5 Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost 
certainly be made more generic. But it does allow us to parse something like:

          ldr     r3, [r2, r4]

correctly in Thumb mode.

llvm-svn: 120408
 2010-11-30 07:44:32 +00:00
Owen Anderson e22c7322b8 Correct Thumb2 encodings for a much wider range of loads and stores. 
llvm-svn: 120364
 2010-11-30 00:14:31 +00:00
Owen Anderson 50d662b6cb Provide Thumb2 encodings for basic loads and stores. 
llvm-svn: 120340
 2010-11-29 22:44:32 +00:00
Bill Wendling 232e52cfb7 Add more Thumb encodings. 
llvm-svn: 120279
 2010-11-29 01:07:48 +00:00
Bill Wendling ccba1a8d95 More Thumb encodings. 
llvm-svn: 120278
 2010-11-29 01:00:43 +00:00
Bill Wendling 9600e97c60 Add Thumb encodings for REV instructions. 
llvm-svn: 120277
 2010-11-29 00:42:50 +00:00
Bill Wendling 775899eb2e Add more Thumb encodings. 
llvm-svn: 120272
 2010-11-29 00:18:15 +00:00
Bill Wendling c01d679928 Add encoding for ARM "trap" instruction. 
llvm-svn: 119938
 2010-11-21 11:05:29 +00:00
Bill Wendling 945b776b6e Add MC encodings for some Thumb instructions. Test for a few of them. The "bx 
lr" instruction cannot be tested just yet. It requires matching a "condition
code", but adding one of those makes things go south quickly...

llvm-svn: 119774
 2010-11-19 01:33:10 +00:00
Bill Wendling 2063b84297 Add support for parsing the writeback ("!") token. 
llvm-svn: 119761
 2010-11-18 23:43:05 +00:00
Owen Anderson 690fa953e1 More tests. 
llvm-svn: 119756
 2010-11-18 23:30:10 +00:00
Owen Anderson 3517585249 Fix encodings for pkhbt, and fix some tests where I accidentally tested ARM mode instead of Thumb2. 
llvm-svn: 119755
 2010-11-18 23:29:56 +00:00
Owen Anderson 3fec5ff14b More Thumb2 encodings. 
llvm-svn: 119737
 2010-11-18 21:15:19 +00:00
Owen Anderson 3625098459 Fill out the set of Thumb2 multiplication operator encodings. 
llvm-svn: 119733
 2010-11-18 20:32:18 +00:00
Owen Anderson d127e7174b Try again at providing Thumb2 encodings for basic multiplication operators. 
llvm-svn: 119601
 2010-11-18 01:08:42 +00:00
Owen Anderson 28883834e1 Revert r119593 while I figure out my testing disagrees with the buildbot. 
llvm-svn: 119597
 2010-11-18 00:42:51 +00:00
Owen Anderson 64aaddcd64 Provide correct Thumb2 encodings for basic multiplication operators. 
llvm-svn: 119593
 2010-11-18 00:19:10 +00:00
Owen Anderson 55425e7f78 Second attempt at correct encodings for Thumb2 bitfield instructions. 
llvm-svn: 119575
 2010-11-17 22:16:31 +00:00