Craig Topper
|
650a15e2b3
|
[X86] Add more opcodes to isFrameLoadOpcode/isFrameStoreOpcode. Mainly AVX-512 related.
llvm-svn: 275764
|
2016-07-18 06:14:39 +00:00 |
|
Craig Topper
|
e5ce84a33c
|
[AVX512] Add VLX 128/256-bit SET0 operations that encode to 128/256-bit EVEX encoded VPXORD so all 32 registers can be used.
llvm-svn: 268884
|
2016-05-08 21:33:53 +00:00 |
|
Igor Breger
|
131008fbcb
|
Change AVX512 braodcastsd/ss patterns interaction with spilling . New implementation take a scalar register and generate a vector without COPY_TO_REGCLASS (turn it into a VR128 register ) .The issue is that during register allocation we may spill a scalar value using 128-bit loads and stores, wasting cache bandwidth.
Differential Revision: http://reviews.llvm.org/D19579
llvm-svn: 268190
|
2016-05-01 08:40:00 +00:00 |