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1484 Commits

Author SHA1 Message Date
Evan Cheng c66fd44541 Add an entry 
llvm-svn: 26520
 2006-03-04 07:49:50 +00:00
Evan Cheng 6dc73297c3 MEMSET / MEMCPY lowering bugs: we can't issue a single WORD / DWORD version of 
rep/stos and rep/mov if the count is not a constant. We could do
  rep/stosl; and $count, 3; rep/stosb
For now, I will lower them to memset / memcpy calls. We will revisit this after
a little bit experiment.

Also need to take care of the trailing bytes even if the count is a constant.
Since the max. number of trailing bytes are 3, we will simply issue loads /
stores.

llvm-svn: 26517
 2006-03-04 02:48:56 +00:00
Evan Cheng 084a102b17 Typo 
llvm-svn: 26512
 2006-03-04 01:12:00 +00:00
Chris Lattner ad3c974a77 remove the read/write port/io intrinsics. 
llvm-svn: 26479
 2006-03-03 00:19:58 +00:00
Evan Cheng 1926427351 Vector op lowering. 
llvm-svn: 26438
 2006-03-01 01:11:20 +00:00
Evan Cheng 0e69f45b07 Another entry. 
llvm-svn: 26430
 2006-02-28 23:38:49 +00:00
Evan Cheng 990c3602bd Don't match x << 1 to LEAL. It's better to emit x + x. 
llvm-svn: 26429
 2006-02-28 21:13:57 +00:00
Evan Cheng 877ab55e06 ConstantPoolIndex is now the displacement portion of the address (rather 
than base).

llvm-svn: 26382
 2006-02-26 09:12:34 +00:00
Evan Cheng 75b8783aaf Fixed ConstantPoolIndex operand asm print bug. This fixed 2005-07-17-INT-To-FP 
and 2005-05-12-Int64ToFP.

llvm-svn: 26380
 2006-02-26 08:28:12 +00:00
Evan Cheng 77d86ff8fc * Cleaned up addressing mode matching code. 
* Cleaned up and tweaked LEA cost analysis code. Removed some hacks.
* Handle ADD $X, c to MOV32ri $X+c. These patterns cannot be autogen'd and
  they need to be matched before LEA.

llvm-svn: 26376
 2006-02-25 10:09:08 +00:00
Evan Cheng 1c557bfeb5 Updates. 
llvm-svn: 26375
 2006-02-25 10:04:07 +00:00
Evan Cheng 1fac3b3360 * Allow mul, shl nodes to be codegen'd as LEA (if appropriate). 
* Add patterns to handle GlobalAddress, ConstantPool, etc.
  MOV32ri to materialize these nodes in registers.
  ADD32ri to handle %reg + GA, etc.
  MOV32mi to handle store GA, etc. to memory.

llvm-svn: 26374
 2006-02-25 10:02:21 +00:00
Evan Cheng e4a8b74e4f ConstantPoolIndex is now the displacement field of addressing mode. 
llvm-svn: 26373
 2006-02-25 09:56:50 +00:00
Evan Cheng 994700101e Added a common about the need for X86ISD::Wrapper. 
llvm-svn: 26372
 2006-02-25 09:55:19 +00:00
Evan Cheng ed169db8a5 Added an offset field to ConstantPoolSDNode. 
llvm-svn: 26371
 2006-02-25 09:54:52 +00:00
Evan Cheng 42d5ac557c Fix an obvious bug exposed when we are doing 
ADD X, 4
==>
MOV32ri $X+4, ...

llvm-svn: 26366
 2006-02-25 01:37:02 +00:00
Evan Cheng e0ed6ec13f - Clean up the lowering and selection code of ConstantPool, GlobalAddress, 
and ExternalSymbol.
- Use C++ code (rather than tblgen'd selection code) to match the above
  mentioned leaf nodes. Do not mutate and nodes and do not record the
  selection in CodeGenMap. These nodes should be safe to duplicate. This is
  a performance win.

llvm-svn: 26335
 2006-02-23 20:41:18 +00:00
Chris Lattner 16f08f53b1 "." isn't enough to get a private label on linux, use ".L". 
llvm-svn: 26327
 2006-02-23 05:25:02 +00:00
Chris Lattner 2bacf981bf add a small and simple case. 
llvm-svn: 26326
 2006-02-23 05:17:43 +00:00
Evan Cheng f4448cee66 A couple of new entries. 
llvm-svn: 26325
 2006-02-23 02:50:21 +00:00
Evan Cheng 1f342c2884 PIC related bug fixes. 
1. Various asm printer bug.
2. Lowering bug. Now TargetGlobalAddress is wrapped in X86ISD::TGAWrapper.

llvm-svn: 26324
 2006-02-23 02:43:52 +00:00
Evan Cheng 7eabbfd618 X86 codegen tweak to use lea in another case: 
Suppose base == %eax and it has multiple uses, then instead of
  movl %eax, %ecx
  addl $8, %ecx
use
  leal 8(%eax), %ecx.

llvm-svn: 26323
 2006-02-23 00:13:58 +00:00
Evan Cheng 7714a59d91 Missing .globl for weak / link-once .text symbols. 
llvm-svn: 26321
 2006-02-22 23:59:57 +00:00
Evan Cheng 73136dfecc - Added option -relocation-model to set relocation model. Valid values include static, pic, 
dynamic-no-pic, and default.
PPC and x86 default is dynamic-no-pic for Darwin, pic for others.
- Removed options -enable-pic and -ppc-static.

llvm-svn: 26315
 2006-02-22 20:19:42 +00:00
Evan Cheng 9e252e3bcf Added MMX, SSE1, and SSE2 vector instructions and some simple patterns. 
Fixed some existing bugs (wrong predicates, prefixes) at the same time.

llvm-svn: 26310
 2006-02-22 02:26:30 +00:00
Chris Lattner 7ad77dfc2a split register class handling from explicit physreg handling. 
llvm-svn: 26308
 2006-02-22 00:56:39 +00:00
Chris Lattner 7bb4696dc3 Updates to match change of getRegForInlineAsmConstraint prototype 
llvm-svn: 26305
 2006-02-21 23:11:00 +00:00
Evan Cheng d58478161f One more round of reorg so sabre doesn't freak out. :-) 
llvm-svn: 26303
 2006-02-21 20:00:20 +00:00
Evan Cheng 6fc1162855 A big more cleaning up. 
llvm-svn: 26302
 2006-02-21 19:30:30 +00:00
Evan Cheng 8711b6bff3 Moving things to their proper places. 
llvm-svn: 26301
 2006-02-21 19:26:52 +00:00
Evan Cheng 6e595b9fd8 Split instruction info into multiple files, one for each of x87, MMX, and SSE. 
llvm-svn: 26300
 2006-02-21 19:13:53 +00:00
Evan Cheng d57203c0a1 Added separate alias instructions for SSE logical ops that operate on non-packed types. 
llvm-svn: 26297
 2006-02-21 02:24:38 +00:00
Evan Cheng afffe63fc1 Added MMX and XMM packed integer move instructions, movd and movq. 
llvm-svn: 26296
 2006-02-21 01:39:57 +00:00
Evan Cheng fa57a0add9 Added SSE2 128-bit integer packed types: V16I8, V8I16, V4I32, and V2I64. 
Added generic vector types: VR64 and VR128.

llvm-svn: 26295
 2006-02-21 01:38:21 +00:00
Evan Cheng 43070b7541 Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit 
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).

llvm-svn: 26294
 2006-02-20 22:34:53 +00:00
Evan Cheng 4547400ae2 Some updates 
llvm-svn: 26292
 2006-02-20 19:58:27 +00:00
Evan Cheng d13778eb30 If SSE3 is available, promote FP_TO_UINT i32 to FP_TO_SINT i64 to take 
advantage of fisttpll.

llvm-svn: 26288
 2006-02-18 07:26:17 +00:00
Evan Cheng 70af620709 Added fisttp for fp to int conversion. 
llvm-svn: 26283
 2006-02-18 02:36:28 +00:00
Evan Cheng 06c2e6d1b3 Disable PIC for JIT. 
llvm-svn: 26281
 2006-02-18 01:49:25 +00:00
Evan Cheng 5caed8a231 Jit does not support PIC yet. 
llvm-svn: 26278
 2006-02-18 00:57:10 +00:00
Evan Cheng 5588de9415 x86 / Darwin PIC support. 
llvm-svn: 26273
 2006-02-18 00:15:05 +00:00
Chris Lattner 07a2677e43 unbreak the build 
llvm-svn: 26260
 2006-02-17 07:09:27 +00:00
Evan Cheng 593bea73ba Unbreak x86 be 
llvm-svn: 26259
 2006-02-17 07:01:52 +00:00
Nate Begeman 5965bd19f8 kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC 
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.

llvm-svn: 26255
 2006-02-17 05:43:56 +00:00
Chris Lattner 67c21b6c46 add note about div by power of 2 
llvm-svn: 26253
 2006-02-17 04:20:13 +00:00
Evan Cheng b590d3a72b Remind ourselves to revisit the "pxor vs. xorps/xorpd to clear XMM registers" 
issue. Need to do more experiments.

llvm-svn: 26247
 2006-02-17 00:04:28 +00:00
Nate Begeman 7e5496d5fe Kill the x86 pattern isel. boom. 
llvm-svn: 26246
 2006-02-17 00:03:04 +00:00
Evan Cheng db1dbbe8d6 Remove the entry about using movapd for SSE reg-reg moves. 
llvm-svn: 26245
 2006-02-17 00:00:58 +00:00
Evan Cheng eb7b3380fd pxor (for FLD0SS) encoding was missing the OpSize prefix. 
llvm-svn: 26244
 2006-02-16 23:59:30 +00:00
Evan Cheng 24c461b51e 1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. This 
proves to be worth 20% on Ptrdist/ks. Might be related to dependency
   breaking support.
2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These
   are used for FR32 / FR64 reg-to-reg copies.
3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to
   spill / restore FsMOVAPSrr and FsMOVAPDrr.

llvm-svn: 26241
 2006-02-16 22:45:17 +00:00