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148 Commits

Author SHA1 Message Date
Owen Anderson ce2250fba4 Fill out support for Thumb2 encodings of NEON instructions. 
llvm-svn: 118854
 2010-11-11 23:12:55 +00:00
Owen Anderson 99a8cb4875 Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4]. 
llvm-svn: 118843
 2010-11-11 21:36:43 +00:00
Owen Anderson a56a2e1fc5 Flesh out tests for Thumb2 encodings of NEON instructions. 
llvm-svn: 118837
 2010-11-11 21:15:47 +00:00
Owen Anderson 7ffe3b35ac Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure. 
More tests to come.

llvm-svn: 118819
 2010-11-11 19:07:48 +00:00
Owen Anderson c7baee31ad Add support for ARM's specialized vector-compare-against-zero instructions. 
llvm-svn: 118453
 2010-11-08 23:21:22 +00:00
Owen Anderson 30c4892ea5 Add codegen and encoding support for the immediate form of vbic. 
llvm-svn: 118291
 2010-11-05 19:27:46 +00:00
Bill Wendling c002463ac4 Add encoding for VSTR. 
llvm-svn: 118220
 2010-11-04 00:59:42 +00:00
Owen Anderson bc9b31c493 Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization. 
This is both the conceptually correct place for it, as well as allowing it to be more aggressive.

llvm-svn: 118204
 2010-11-03 23:15:26 +00:00
Owen Anderson 0747307049 Add support for code generation of the one register with immediate form of vorr. 
We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.

llvm-svn: 118201
 2010-11-03 22:44:51 +00:00
Owen Anderson bb81f80af6 Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead, 
all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.

llvm-svn: 118183
 2010-11-03 18:16:27 +00:00
Bill Wendling e84eb99cbb The MC code couldn't handle ARM LDR instructions with negative offsets: 
vldr.64 d1, [r0, #-32]

The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.

llvm-svn: 118144
 2010-11-03 01:49:29 +00:00
Bill Wendling 603bd8f54c Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work 
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.

llvm-svn: 118094
 2010-11-02 22:31:46 +00:00
Owen Anderson dec87e10fd Provide correct encodings for the remaining vst variants that we currently generate. 
llvm-svn: 118087
 2010-11-02 22:18:18 +00:00
Owen Anderson b95618cfe0 Add correct encodings for basic variants for vst3 and vst4. 
llvm-svn: 118082
 2010-11-02 21:47:03 +00:00
Owen Anderson fa08e1e277 Add correct encodings for the basic variants for vst2. 
llvm-svn: 118068
 2010-11-02 21:16:58 +00:00
Owen Anderson 87c62e54e6 Add correct encodings for the basic form of vst1. 
llvm-svn: 118067
 2010-11-02 21:06:06 +00:00
Owen Anderson a83859539f Add correct encodings for the rest of the vld instructions that we generate. 
llvm-svn: 118053
 2010-11-02 20:40:59 +00:00
Owen Anderson 526ffd57d2 Add correct NEON encodings for vld2, vld3, and vld4 basic variants. 
llvm-svn: 117997
 2010-11-02 01:24:55 +00:00
Owen Anderson ad40234eff Add correct NEON encodings for the "multiple single elements" form of vld. 
llvm-svn: 117984
 2010-11-02 00:05:05 +00:00
Bill Wendling 793af5fa07 Use ARM-style comments. 
llvm-svn: 117955
 2010-11-01 21:16:39 +00:00
Owen Anderson cd9da22f68 Use ARM-style comment syntax. 
llvm-svn: 117941
 2010-11-01 18:33:37 +00:00
Owen Anderson 083ddf7d6a Covert this test to .s form. 
llvm-svn: 117939
 2010-11-01 18:30:39 +00:00
Owen Anderson a7d985738c Convert this test to .s form. 
llvm-svn: 117938
 2010-11-01 18:26:43 +00:00
Owen Anderson e5271a935a Covert this test to .s form. 
llvm-svn: 117937
 2010-11-01 18:13:11 +00:00
Owen Anderson 051b7893dd Covert this test to .s form. 
llvm-svn: 117935
 2010-11-01 18:03:16 +00:00
Jim Grosbach 0190a649e8 Mark ARM subtarget features that are available for the assembler. 
llvm-svn: 117929
 2010-11-01 16:59:54 +00:00
Owen Anderson fccb9d032f Convert this test to .s form. 
llvm-svn: 117900
 2010-11-01 05:23:58 +00:00
Bill Wendling 193961bb1a Some instructions end with an "ls" prefix, but it doesn't indicate that they are 
conditional. Check for those instructions explicitly.

llvm-svn: 117747
 2010-10-29 23:50:21 +00:00
Owen Anderson 72dfc6a7c7 Convert this test to .s form. 
llvm-svn: 117708
 2010-10-29 20:39:19 +00:00
Owen Anderson 665b9e37ff Convert this test to .s form. 
llvm-svn: 117704
 2010-10-29 20:23:45 +00:00
Owen Anderson fe4b52a066 Convert this test to .s form. 
llvm-svn: 117699
 2010-10-29 20:17:07 +00:00
Owen Anderson 0093f9a634 Convert this test to .s form. 
llvm-svn: 117696
 2010-10-29 20:12:34 +00:00
Owen Anderson ede9d861db Covert this test to .s form. 
llvm-svn: 117694
 2010-10-29 19:56:07 +00:00
Owen Anderson 6f9cd06ff9 Convert this test to .s form. 
llvm-svn: 117693
 2010-10-29 19:51:11 +00:00
Owen Anderson 3ad831ac77 Convert this test to .s form. 
llvm-svn: 117690
 2010-10-29 19:45:32 +00:00
Owen Anderson 302596e5e1 Convert this test to .s form. 
llvm-svn: 117689
 2010-10-29 19:37:05 +00:00
Owen Anderson efdf57afdc Convert this test to .s form. 
llvm-svn: 117686
 2010-10-29 19:17:08 +00:00
Owen Anderson 221b524fe1 Convert this test to .s form. 
llvm-svn: 117685
 2010-10-29 19:09:08 +00:00
Owen Anderson b916206545 Covert this test to .s form. 
llvm-svn: 117684
 2010-10-29 19:05:26 +00:00
Owen Anderson 733d1b1a60 Convert this test to .s form. 
llvm-svn: 117683
 2010-10-29 18:58:30 +00:00
Owen Anderson 7d23a78188 Convert this test to .s form. 
llvm-svn: 117682
 2010-10-29 18:48:59 +00:00
Owen Anderson 7eed15242d Convert this file to less fragile .s form. 
llvm-svn: 117681
 2010-10-29 18:41:40 +00:00
Owen Anderson 13ff53e7b6 Replace this test with the less fragile .s version. Still XFAIL'd, since the ASM parser doesn't parse vabal yet. 
llvm-svn: 117679
 2010-10-29 18:31:26 +00:00
Owen Anderson 66aa87021c Covert this test to a .s file to reduce fragility. 
llvm-svn: 117676
 2010-10-29 18:18:40 +00:00
Owen Anderson b101af04b4 Convert this test to a .s file, so that it's not sensitive to codegen changes. 
llvm-svn: 117633
 2010-10-29 01:01:56 +00:00
Chris Lattner 5d6f6a061b add simple support for addrmode5 operands, allowing 
vldr.64 to work.  I have no idea if this is fully right, but 
it is in the right direction.

llvm-svn: 117626
 2010-10-29 00:27:31 +00:00
Chris Lattner 327a61423b most simple arm instructions match correctly now, 
it looks like we're not handling [] operands though

llvm-svn: 117607
 2010-10-28 21:31:07 +00:00
Chris Lattner 1be0697ab9 fix the asmmatcher generator to handle targets with no RegisterPrefix 
(like ARM) correctly.  With this change, we can now match "bx lr"
because we recognize lr as a register.

llvm-svn: 117606
 2010-10-28 21:28:42 +00:00
Evan Cheng 0165e25564 Disable most of the ARM vfp / NEON MC tests. These are too fragile to be useful. 
I'll work with Jim, Owen, and Bill on an alternative testing strategy until
the assembly parser is available.

llvm-svn: 117530
 2010-10-28 06:46:17 +00:00
Owen Anderson 2ef668840a Add correct NEON encodings for vtbl and vtbx. 
llvm-svn: 117513
 2010-10-28 00:18:46 +00:00