Commit Graph

94 Commits

Author SHA1 Message Date
Stanislav Mekhanoshin 22b2c3d651 [AMDGPU] gfx908 target
Differential Revision: https://reviews.llvm.org/D64429

llvm-svn: 365525
2019-07-09 18:10:06 +00:00
Dmitry Preobrazhensky 463b87ae88 [AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description.
Corrected a typo.

llvm-svn: 365353
2019-07-08 17:09:09 +00:00
Dmitry Preobrazhensky cef9d42157 [AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description.
Summary of changes:
- added description of GFX10;
- added description of operands sccz, vccz, lds_direct, etc;
- minor bugfixing and improvements.

llvm-svn: 365347
2019-07-08 16:50:11 +00:00
Yaxun Liu a62413526d [AMDGPU] Added a new metadata for multi grid sync implicit argument
Patch by Christudasan Devadasan.

Differential Revision: https://reviews.llvm.org/D63886

llvm-svn: 365217
2019-07-05 16:05:17 +00:00
Nicolai Haehnle 08e8cb5760 AMDGPU/MC: Add .amdgpu_lds directive
Summary:
The directive defines a symbol as an group/local memory (LDS) symbol.
LDS symbols behave similar to common symbols for the purposes of ELF,
using the processor-specific SHN_AMDGPU_LDS as section index.

It is the linker and/or runtime loader's job to "instantiate" LDS symbols
and resolve relocations that reference them.

It is not possible to initialize LDS memory (not even zero-initialize
as for .bss).

We want to be able to link together objects -- starting with relocatable
objects, but possible expanding to shared objects in the future -- that
access LDS memory in a flexible way.

LDS memory is in an address space that is entirely separate from the
address space that contains the program image (code and normal data),
so having program segments for it doesn't really make sense.

Furthermore, we want to be able to compile multiple kernels in a
compilation unit which have disjoint use of LDS memory. In that case,
we may want to place LDS symbols differently for different kernels
to save memory (LDS memory is very limited and physically private to
each kernel invocation), so we can't simply place LDS symbols in a
.lds section.

Hence this solution where LDS symbols always stay undefined.

Change-Id: I08cbc37a7c0c32f53f7b6123aa0afc91dbc1748f

Reviewers: arsenm, rampitec, t-tye, b-sumner, jsjodin

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, rupprecht, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D61493

llvm-svn: 364296
2019-06-25 11:51:35 +00:00
Stanislav Mekhanoshin 4336a9496d [AMDGPU] gfx10 documentation update. NFC.
llvm-svn: 363332
2019-06-13 22:18:47 +00:00
Matt Arsenault 4fb580c314 AMDGPU: Remove amdgpu-max-work-group-size attribute
This has been deprecated for a long time, and mesa recently switched
to amdgpu-flat-work-group-size.

llvm-svn: 362641
2019-06-05 20:32:32 +00:00
Zachary Turner 6eb7ab97a5 Try to fix Sphinx bot.
llvm-svn: 357790
2019-04-05 18:06:42 +00:00
Matt Arsenault 055e4dce45 AMDGPU: Remove dx10-clamp from subtarget features
Since this can be set with s_setreg*, it should not be a subtarget
property. Set a default based on the calling convention, and Introduce
a new amdgpu-dx10-clamp attribute to override this if desired.

Also introduce a new amdgpu-ieee attribute to match.

The values need to match to allow inlining. I think it is OK for the
caller's dx10-clamp attribute to override the callee, but there
doesn't appear to be the infrastructure to do this currently without
definining the attribute in the generic Attributes.td.

Eventually the calling convention lowering will need to insert a mode
switch somewhere for these.

llvm-svn: 357302
2019-03-29 19:14:54 +00:00
Scott Linder 0bc9f15ddd [AMDGPU] Add an additional Code Object V3 assembler example
Document the intended use of the `.amdgcn.next_free_{s,v}gpr` in the
context of multiple kernels and functions.

Differential Revision: https://reviews.llvm.org/D59949

llvm-svn: 357289
2019-03-29 17:49:51 +00:00
Konstantin Zhuravlyov 2b766ed774 AMDGPU: Make sram-ecc off by default for Vega20
Differential Revision: https://reviews.llvm.org/D59718

llvm-svn: 357247
2019-03-29 12:04:18 +00:00
Scott Linder ac20b74573 [AMDGPU] Clarify Code Object V2/V3 differences in AMDGPUUsage
Ensure Code Object V2 documentation is complete, but always contains a
warning and a link to the equivalent Code Object V3 documentation.

Explicitly indicate that any note records present in a code object that
are not documented must be considered deprecated and ignored.

Differential Revision: https://reviews.llvm.org/D59782

llvm-svn: 357176
2019-03-28 15:08:52 +00:00
Konstantin Zhuravlyov 51809cbc98 AMDGPU: Add support for cross address space synchronization scopes
Differential Revision: https://reviews.llvm.org/D59517

llvm-svn: 356946
2019-03-25 20:50:21 +00:00
Neil Henning 523dab0788 [AMDGPU] Add an experimental buffer fat pointer address space.
Add an experimental buffer fat pointer address space that is currently
unhandled in the backend. This commit reserves address space 7 as a
non-integral pointer repsenting the 160-bit fat pointer (128-bit buffer
descriptor + 32-bit offset) that is heavily used in graphics workloads
using the AMDGPU backend.

Differential Revision: https://reviews.llvm.org/D58957

llvm-svn: 356373
2019-03-18 14:44:28 +00:00
Dmitry Preobrazhensky 62a0318dff [AMDGPU][MC][CODEOBJECT] Added predefined symbols to access GPU minor and stepping numbers
Added the following Code Object v3 symbols:
    .amdgcn.gfx_generation_minor
    .amdgcn.gfx_generation_stepping

Reviewers: artem.tamazov, kzhuravl

Differential Revision: https://reviews.llvm.org/D57826

llvm-svn: 353515
2019-02-08 13:51:31 +00:00
Dmitry Preobrazhensky 47eb63684d [AMDGPU][MC][DOC] Updated AMD GPU assembler description
Stage 2: added detailed description of operands

See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572

llvm-svn: 349368
2018-12-17 17:38:11 +00:00
Scott Linder 8d5a36a839 [AMDGPU] Update code object metadata format documentation
* Add amdhsa prefix to names to allow other tools to use the metadata
  without collision.
* Make names consistent.
* Simplify structure.
* Change note record ID.
* Switch from YAML to MsgPack format.
* Document metadata assembler directive.

Patch By: t-tye (Tony Tye)
Differential Revision: https://reviews.llvm.org/D53445

llvm-svn: 346992
2018-11-15 20:46:55 +00:00
Konstantin Zhuravlyov 3c5d23912b AMDGPU/Docs: Add product names for Vega20
Differential Revision: https://reviews.llvm.org/D54178

llvm-svn: 346354
2018-11-07 20:54:16 +00:00
Konstantin Zhuravlyov b44b890100 AMDGPU/Docs: Fix the processor table
llvm-svn: 346263
2018-11-06 20:23:53 +00:00
Konstantin Zhuravlyov 108927b944 AMDGPU: Add sram-ecc feature
Differential Revision: https://reviews.llvm.org/D53222

llvm-svn: 346177
2018-11-05 22:44:19 +00:00
Tim Renouf 2a1b1d94b6 [AMDGPU] Defined gfx909 Raven Ridge 2
Differential Revision: https://reviews.llvm.org/D53418

Change-Id: Ie3d054f2e956c2768988c0f4c0ffd29a47294eef
llvm-svn: 345120
2018-10-24 08:14:07 +00:00
Chandler Carruth 343a87ac8d [docs] Turn of `nasm` highlighting for a code block.
This appears to produce a warning on the docs build bot. It doesn't
reproduce for me, likely because I have a newer (or more full featured)
pygments install.

llvm-svn: 338978
2018-08-06 01:19:43 +00:00
Konstantin Zhuravlyov dd6b05c34c AMDHSA: Put old assembler docs back
Until we switch to code object v3 by default.
Follow up for https://reviews.llvm.org/D47736.

Differential Revision: https://reviews.llvm.org/D48497

llvm-svn: 335378
2018-06-22 19:23:18 +00:00
Scott Linder 1e8c2c705d [AMDGPU] Update assembler for HSA Code Object v3
Update AMDGPU assembler syntax behind the code-object-v3 feature:

* Replace/rename most AMDGPU assembler directives/symbols and document them.
* Provide more diagnostics (e.g. values out of range, missing values, repeated
  values).
* Provide path for backwards compatibility, even with underlying descriptor
  changes.

Differential Revision: https://reviews.llvm.org/D47736

llvm-svn: 335281
2018-06-21 19:38:56 +00:00
Konstantin Zhuravlyov 766c77efd7 AMDGPU/AMDHSA: Remove GridWorkGroupCountX/Y/Z
and everything that comes with it from implementation
and v3 header files.

Leave definition in v2 header files for backwards
compatibility.

Differential Revision: https://reviews.llvm.org/D48191

llvm-svn: 335267
2018-06-21 18:36:04 +00:00
Tony Tye e2f3e10913 [AMDGPU] Document the AMDGPU LLVM attributes
Differential Revision: https://reviews.llvm.org/D48101

llvm-svn: 334733
2018-06-14 16:40:10 +00:00
Konstantin Zhuravlyov 00f2cb1116 AMDHSA: Code object v3 updates
- Do not emit following assembler directives:
  - .hsa_code_object_version
  - .hsa_code_object_isa
  - .amd_amdgpu_isa
  - .amd_amdgpu_hsa_metadata
  - .amd_amdgpu_pal_metadata
- Do not emit .note entries
- Cleanup and bring in sync kernel descriptor header file
- Emit kernel descriptor into .rodata with appropriate relocations and
  alignments

llvm-svn: 334519
2018-06-12 18:02:46 +00:00
Konstantin Zhuravlyov 2ca6b1f2ba AMDGPU: Always set COMPUTE_PGM_RSRC2.ENABLE_TRAP_HANDLER to zero for AMDHSA as
it is set by CP

Differential Revision: https://reviews.llvm.org/D47392

llvm-svn: 333451
2018-05-29 19:09:13 +00:00
Tony Tye 43259df44a [AMDGPU] Change llvm.debugtrap to be a debug breakpoint that can resume execution.
No longer require the queue pointer to be passed in in fixed SGPRs.

Differential Revision: https://reviews.llvm.org/D46769

llvm-svn: 332485
2018-05-16 16:19:34 +00:00
Matt Arsenault 0084adc516 AMDGPU: Add Vega12 and Vega20
Changes by
  Matt Arsenault
  Konstantin Zhuravlyov

llvm-svn: 331215
2018-04-30 19:08:16 +00:00
Tony Tye b6efb90717 [AMDGPU] Add gfx902 product names
Differential Revision: https://reviews.llvm.org/D45609

llvm-svn: 330081
2018-04-14 01:58:10 +00:00
Tony Tye 223f4c7c99 [AMDGPU] Update relocation record description
Document which relocation records are static and dynamic.

Differential Revision: https://reviews.llvm.org/D45587

llvm-svn: 329981
2018-04-13 01:01:27 +00:00
Hiroshi Inoue bcadfee2ad [NFC] fix trivial typos in documents and comments
"is is" -> "is", "if if" -> "if", "or or" -> "or"

llvm-svn: 329878
2018-04-12 05:53:20 +00:00
Tim Corringham af2dfc697b Add AMDPAL Code Conventions section to AMD docs
Summary:
This is a first version of the AMDPAL code conventions.
Further updates will undoubtably be required to fully
document AMDPAL.

Subscribers: nhaehnle, llvm-commits

Differential Revision: https://reviews.llvm.org/D45246

llvm-svn: 329188
2018-04-04 13:02:09 +00:00
Tony Tye 01bfd6c4e5 [AMDGPU] Define code object identification string used in AMDHSA runtimes.
Differential Revision: https://reviews.llvm.org/D44718

llvm-svn: 328669
2018-03-27 21:20:46 +00:00
Tony Tye 88441a3d1e [AMDGPU] Update OpenCL to use 48 bytes of implicit arguments for AMDGPU
Add two additional implicit arguments for OpenCL for the AMDGPU target using the AMDHSA runtime to support device enqueue.

Differential Revision: https://reviews.llvm.org/D44697

llvm-svn: 328351
2018-03-23 18:58:47 +00:00
Tony Tye 7a893d4e34 [AMDGPU] Remove use of OpenCL triple environment and replace with function attribute for AMDGPU
- Remove use of the opencl and amdopencl environment member of the target triple for the AMDGPU target.
- Use function attribute to communicate to the AMDGPU backend to add implicit arguments for OpenCL kernels for the AMDHSA OS.

Differential Revision: https://reviews.llvm.org/D43736

llvm-svn: 328349
2018-03-23 18:45:18 +00:00
Eugene Zelenko 3507b0489f [Documentation] Fix markup problem in AMDGPUUsage.rst.
llvm-svn: 328116
2018-03-21 17:09:35 +00:00
Craig Topper b5ed275025 [TableGen] Pass result of std::unique to vector::erase instead of calculating a size and calling resize.
llvm-svn: 328031
2018-03-20 20:24:10 +00:00
Dmitry Preobrazhensky c6d31e6f4e [AMDGPU][MC][DOC] Updated AMD GPU assembler description
See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572

Differential Revision: https://reviews.llvm.org/D44020

Reviewers: artem.tamazov, vpykhtin
llvm-svn: 327288
2018-03-12 15:55:08 +00:00
Tony Tye 5bbcca6967 [AMDGPU] Update AMDGOUUsage.rst descriptions
- Improve description of XNACK ELF flag.
- Rename all uses of wave to wavefront to be consistent.

Differential Revision: https://reviews.llvm.org/D43983

llvm-svn: 326989
2018-03-08 05:46:01 +00:00
Scott Linder 16c7bdaf32 [DebugInfo] Support DWARF v5 source code embedding extension
In DWARF v5 the Line Number Program Header is extensible, allowing values with
new content types. In this extension a content type is added,
DW_LNCT_LLVM_source, which contains the embedded source code of the file.

Add new optional attribute for !DIFile IR metadata called source which contains
source text. Use this to output the source to the DWARF line table of code
objects. Analogously extend METADATA_FILE in Bitcode and .file directive in ASM
to support optional source.

Teach llvm-dwarfdump and llvm-objdump about the new values. Update the output
format of llvm-dwarfdump to make room for the new attribute on file_names
entries, and support embedded sources for the -source option in llvm-objdump.

Differential Revision: https://reviews.llvm.org/D42765

llvm-svn: 325970
2018-02-23 23:01:06 +00:00
Konstantin Zhuravlyov 9122a63143 AMDGPU: Bring elf flags in sync with the spec
- Add MACH flags
- Add XNACK flag
- Add reserved flags
- Minor cleanups in docs

Differential Revision: https://reviews.llvm.org/D43356

llvm-svn: 325399
2018-02-16 22:33:59 +00:00
Yaxun Liu 0124b5484c [AMDGPU] Change constant addr space to 4
Differential Revision: https://reviews.llvm.org/D43170

llvm-svn: 325030
2018-02-13 18:00:25 +00:00
Matt Arsenault 923712b6b5 Reapply "AMDGPU: Add 32-bit constant address space"
This reverts r324494 and reapplies r324487.

llvm-svn: 324747
2018-02-09 16:57:57 +00:00
Yaxun Liu 976f317f0c [AMDGPU] Updae documentation about address space
llvm-svn: 324617
2018-02-08 15:41:19 +00:00
Rafael Espindola f4e3f3e31c Revert "AMDGPU: Add 32-bit constant address space"
This reverts commit r324487.

It broke clang tests.

llvm-svn: 324494
2018-02-07 18:09:35 +00:00
Marek Olsak 871c30e540 AMDGPU: Add 32-bit constant address space
Note: This is a candidate for LLVM 6.0, because it was planned to be
      in that release but was delayed due to a long review period.

Merge conflict in release_60 - resolution:
    Add "-p6:32:32" into the second (non-amdgiz) string.

Only scalar loads support 32-bit pointers. An address in a VGPR will
fail to compile. That's OK because the results of loads will only be used
in places where VGPRs are forbidden.

Updated AMDGPUAliasAnalysis and used SReg_64_XEXEC.
The tests cover all uses cases we need for Mesa.

Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D41651

llvm-svn: 324487
2018-02-07 16:01:00 +00:00
Tony Tye db6c993faf [AMDGPU] Update relocation documentation and elf flag machine architecture numbers
Differential Revision: https://reviews.llvm.org/D42714

llvm-svn: 323835
2018-01-30 23:59:43 +00:00
Tony Tye e039d0ee12 [AMDGPU] Clarify ReqdWorkGroupSize and MaxFlatWorkGroupSize metadata
- If ReqdWorkGroupSize is present it must have all elements >=1.
- If MaxFlatWorkGroupSize must be consistent with ReqdWorkGroupSize.
- Remove FixedWorkGroupSize as now equivalent to ReqdWorkGroupSize.

llvm-svn: 323829
2018-01-30 23:07:10 +00:00