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64 Commits

Author SHA1 Message Date
Hao Liu ba38eee8ac AArch64: The pattern match should check the range of the immediate value. 
Or we can generate some illegal instructions.
E.g. shrn2 v0.4s, v1.2d, #35. The legal range should be in [1, 16].

llvm-svn: 195941
 2013-11-29 02:11:22 +00:00
Jiangning Liu c429c00f3b Add missing pattern for supporting intrinsic function vbsl_f64 with 
argument double floating point.

llvm-svn: 195938
 2013-11-29 01:37:15 +00:00
Kevin Qin 337cfcc83c [AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction. 
llvm-svn: 195936
 2013-11-29 01:29:16 +00:00
Jiangning Liu 97aa8cf8b7 Fix the AArch64 NEON bug exposed by checking constant integer argument range of ACLE intrinsics. 
llvm-svn: 195843
 2013-11-27 14:02:25 +00:00
Chad Rosier 75290c6307 [AArch64] Add support for NEON scalar floating-point absolute difference. 
llvm-svn: 195803
 2013-11-27 01:45:58 +00:00
Chad Rosier 9653d5c989 [AArch64] Add support for NEON scalar floating-point to integer convert 
instructions.

llvm-svn: 195788
 2013-11-26 22:17:37 +00:00
Kevin Qin 599c47d0de Refactored the implementation of AArch64 NEON instruction ZIP, UZP 
and TRN.
Fix a bug when mixed use of vget_high_u8() and vuzp_u8().

llvm-svn: 195716
 2013-11-26 03:26:47 +00:00
Hao Liu 25aed9bb5b Fix the bugs about AArch64 Load/Store vector types and bitcast between i64 and vector types. 
e.g. "%tmp = load <2 x i64>* %ptr" can't be selected. 
     "%tmp = bitcast i64 %in to <2 x i32>" can't be selected.

llvm-svn: 195424
 2013-11-22 08:47:22 +00:00
Jiangning Liu a91633a435 For AArch64 back-end instruction selection, lower Neon_Lowxxx with EXTRCT_SUBREG. 
llvm-svn: 195408
 2013-11-22 02:45:13 +00:00
Ana Pazos 9ac2fc85d2 Implemented Neon scalar vdup_lane intrinsics. 
Fixed scalar dup alias and added test case.

llvm-svn: 195330
 2013-11-21 08:16:15 +00:00
Ana Pazos fbc1adbaa7 Implemented Neon scalar by element intrinsics. 
Intrinsics implemented: vqdmull_lane, vqdmulh_lane, vqrdmulh_lane,
vqdmlal_lane, vqdmlsl_lane scalar Neon intrinsics.

llvm-svn: 195327
 2013-11-21 07:37:04 +00:00
Hao Liu 16edc4675c Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post. 
llvm-svn: 195078
 2013-11-19 02:17:05 +00:00
Jiangning Liu 0c0c1e8598 Implement AArch64 SISD intrinsics for vget_high and vget_low. 
llvm-svn: 195074
 2013-11-19 01:46:48 +00:00
Kevin Qin 7f8073edc2 implement MC layer of AArch64 neon instruction PMULL and PMULL2 with 128 bit integer. 
llvm-svn: 195072
 2013-11-19 01:40:25 +00:00
Jiangning Liu e329114ae5 Add predicate for AArch64 crypto instructions. 
llvm-svn: 195071
 2013-11-19 01:38:31 +00:00
Kevin Qin 6588c1a638 [AArch64 NEON]Add mov alias for simd copy instructions. 
Set some unspecified bits of INS/DUP to zero as ARMARM requested.

llvm-svn: 194996
 2013-11-18 09:20:32 +00:00
Hao Liu 5a4e4e107d Implement the newly added ACLE functions for ld1/st1 with 2/3/4 vectors. 
The functions are like: vst1_s8_x2 ...

llvm-svn: 194990
 2013-11-18 06:31:53 +00:00
Ana Pazos d035209bd7 Implemented aarch64 Neon scalar vmulx_lane intrinsics 
Implemented aarch64 Neon scalar vfma_lane intrinsics
Implemented aarch64 Neon scalar vfms_lane intrinsics

Implemented legacy vmul_n_f64, vmul_lane_f64, vmul_laneq_f64
intrinsics (v1f64 parameter type) using Neon scalar instructions.

Implemented legacy vfma_lane_f64, vfms_lane_f64,
vfma_laneq_f64, vfms_laneq_f64 intrinsics (v1f64 parameter type)
using Neon scalar instructions.

llvm-svn: 194888
 2013-11-15 23:32:10 +00:00
Chad Rosier 0c57c3402e [AArch64] Fix the scalar NEON ACLE functions so that they return float/double 
rather than the vector equivalent.

llvm-svn: 194853
 2013-11-15 21:28:10 +00:00
Chad Rosier fd675d932c [AArch64] Remove redundant Neon_immAllOnes/Neon_immAllZeros leaf patterns. 
llvm-svn: 194733
 2013-11-14 22:02:46 +00:00
Kevin Qin afc8bdfd57 [AArch64 neon] support poly64 and relevant intrinsic functions. 
llvm-svn: 194659
 2013-11-14 03:27:58 +00:00
Kevin Qin aec95baf1a Implement aarch64 neon instruction class SIMD misc. 
llvm-svn: 194656
 2013-11-14 02:44:13 +00:00
Jiangning Liu bb60ccf355 Implement AArch64 NEON instruction set AdvSIMD (table). 
llvm-svn: 194648
 2013-11-14 01:57:32 +00:00
Chad Rosier d3ae5f895e [AArch64] Add support for legacy AArch32 NEON scalar shift by immediate 
instructions.  This patch does not include the shift right and accumulate
instructions.  A number of non-overloaded intrinsics have been remove in favor
of their overloaded counterparts.

llvm-svn: 194598
 2013-11-13 20:05:37 +00:00
Chad Rosier 1eb0ecf8ce [AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalar 
copy in MC layer. Added the MC layer tests.  Fixed triple setting in test cases.

Patch by Ana Pazos <apazos@codeaurora.org>.

llvm-svn: 194501
 2013-11-12 19:13:08 +00:00
Chad Rosier d3684a0566 [AArch64] The shift right/left and insert immediate builtins expect 3 
source operands, a vector, an element to insert, and a shift amount.

llvm-svn: 194406
 2013-11-11 19:11:11 +00:00
Chad Rosier 35575e737c [AArch64] Add support for NEON scalar floating-point convert to fixed-point instructions. 
llvm-svn: 194394
 2013-11-11 18:04:07 +00:00
Jiangning Liu f4226f1d7b Implement AArch64 Neon instruction set Perm. 
llvm-svn: 194123
 2013-11-06 03:35:27 +00:00
Jiangning Liu a50e22ca4f Implement AArch64 Neon instruction set Bitwise Extract. 
llvm-svn: 194118
 2013-11-06 02:25:49 +00:00
Jiangning Liu d7c52676f6 Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA. 
llvm-svn: 194085
 2013-11-05 17:42:05 +00:00
Hao Liu d6b40b51c7 Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post). 
Including following 14 instructions:
4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 194043
 2013-11-05 03:39:32 +00:00
Kevin Qin 97f6aaa8ad Implemented aarch64 neon intrinsic vcopy_lane with float type. 
llvm-svn: 194041
 2013-11-05 02:03:59 +00:00
Chad Rosier 995d9c2fdc [AArch64] Simplify a few of the instruction patterns. No functional change intended. 
llvm-svn: 193867
 2013-11-01 17:13:44 +00:00
Chad Rosier a4bfb44a9e [AArch64] Fix assembly string formatting and other coding standard violations. 
llvm-svn: 193866
 2013-11-01 17:13:42 +00:00
Chad Rosier 74b65cd811 [AArch64] Add support for NEON scalar fixed-point convert to floating-point instructions. 
llvm-svn: 193816
 2013-10-31 22:36:59 +00:00
Chad Rosier 20e1f20d69 [AArch64] Add support for NEON scalar shift immediate instructions. 
llvm-svn: 193790
 2013-10-31 19:28:44 +00:00
Chad Rosier be020d0309 [AArch64] Add support for NEON scalar floating-point compare instructions. 
llvm-svn: 193691
 2013-10-30 15:19:37 +00:00
Nadav Rotem d369d4bdf9 Optimize concat_vectors(X, undef) -> scalar_to_vector(X). 
This optimization is not SSE specific so I am moving it to DAGco.
The new scalar_to_vector dag node exposed a missing pattern in the AArch64 target that I needed to add.

llvm-svn: 193393
 2013-10-25 06:41:18 +00:00
Chad Rosier e012cb3783 [AArch64] Add the constraint to NEON scalar mla/mls instructions. 
llvm-svn: 193117
 2013-10-21 20:11:47 +00:00
Chad Rosier fe2f58c8a1 [AArch64] Add support for NEON scalar extract narrow instructions. 
llvm-svn: 192970
 2013-10-18 14:03:24 +00:00
Chad Rosier 37d29173aa [AArch64] Add support for NEON scalar three register different instruction 
class.  The instruction class includes the signed saturating doubling
multiply-add long, signed saturating doubling multiply-subtract long, and
the signed saturating doubling multiply long instructions.

llvm-svn: 192908
 2013-10-17 18:12:29 +00:00
Chad Rosier 846a72539c [AArch64] Add support for NEON scalar negate instruction. 
llvm-svn: 192843
 2013-10-16 21:04:39 +00:00
Chad Rosier 175601d997 [AArch64] Add support for NEON scalar absolute value instruction. 
llvm-svn: 192842
 2013-10-16 21:04:34 +00:00
Chad Rosier f2b254558f Fix comment. 
llvm-svn: 192805
 2013-10-16 16:22:15 +00:00
Chad Rosier 178b1cefc7 [AArch64] Add support for NEON scalar signed saturating accumulated of unsigned 
value and unsigned saturating accumulate of signed value instructions.

llvm-svn: 192800
 2013-10-16 16:09:02 +00:00
Chad Rosier 9d51708677 [AArch64] Add support for NEON scalar signed saturating absolute value and 
scalar signed saturating negate instructions.

llvm-svn: 192733
 2013-10-15 21:18:44 +00:00
Chad Rosier d1f40d760a [AArch64] Add support for NEON scalar integer compare instructions. 
llvm-svn: 192596
 2013-10-14 14:37:20 +00:00
Kevin Qin a89e7a0e1c Implement aarch64 neon instruction set AdvSIMD (copy). 
llvm-svn: 192410
 2013-10-11 02:33:55 +00:00
Hao Liu 99eac7ee44 Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). 
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 192361
 2013-10-10 17:00:52 +00:00
Rafael Espindola 9558af461d Revert "Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)." 
This reverts commit r192352. It broke the build.

llvm-svn: 192354
 2013-10-10 15:15:17 +00:00