5 Commits

Author	SHA1	Message	Date
Tom Stellard	0bc954e3bc	AMDGPU/SI: Enable lanemask tracking in misched ... Summary: This results in higher register usage, but should make it easier for the compiler to hide latency. This pass is a prerequisite for some more scheduler improvements, and I think the increase register usage with this patch is acceptable, because when combined with the scheduler improvements, the total register usage will decrease. shader-db stats: 2382 shaders in 478 tests Totals: SGPRS: 48672 -> 49088 (0.85 %) VGPRS: 34148 -> 34847 (2.05 %) Code Size: 1285816 -> 1289128 (0.26 %) bytes LDS: 28 -> 28 (0.00 %) blocks Scratch: 492544 -> 573440 (16.42 %) bytes per wave Max Waves: 6856 -> 6846 (-0.15 %) Wait states: 0 -> 0 (0.00 %) Depends on D18451 Reviewers: nhaehnle, arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18452 llvm-svn: 264876	2016-03-30 16:35:09 +00:00
Matt Arsenault	9c47dd583a	AMDGPU: Remove some old intrinsic uses from tests ... llvm-svn: 260493	2016-02-11 06:02:01 +00:00
Matt Arsenault	10a509292c	Fix broken type legalization of min/max ... This was using an anyext when promoting the type when zext/sext is required. llvm-svn: 256074	2015-12-19 01:39:48 +00:00
Matt Arsenault	fabab4b7dd	SelectionDAG: Match min/max if the scalar operation is legal ... llvm-svn: 255388	2015-12-11 23:16:47 +00:00
Tom Stellard	45bb48ea19	R600 -> AMDGPU rename ... llvm-svn: 239657	2015-06-13 03:28:10 +00:00