Commit Graph

174562 Commits

Author SHA1 Message Date
Juergen Ributzka bcbed0a549 Revert "[PM] Add pass run listeners to the pass manager."
Revert the current implementation and C API. New implementation and C APIs are
in the works.

llvm-svn: 208904
2014-05-15 17:49:20 +00:00
Chandler Carruth 332e1b1909 Exclude MSVC to try to unbreak their builds. We have a bad skew between
how CMake drives a windows link and how our custom command does.

llvm-svn: 208903
2014-05-15 16:33:58 +00:00
Bradley Smith 597122b026 [ARM64] Improve diagnostics for Cn operands in SYS instructions
llvm-svn: 208902
2014-05-15 16:28:32 +00:00
Ben Langmuir ef914b89b4 Use the virtual name of headers when searching for a module
When using the VFS, we want the virtual header location when searching
for a framework module, since that will be the one in the correct
directory structure for the module.

I'll add a regression test once I finish reducing the larger one I have.

llvm-svn: 208901
2014-05-15 16:20:33 +00:00
Simon Atanasyan 73e047e54c [yaml2obj] Add "-o" command line option to specify an output file name.
llvm-svn: 208900
2014-05-15 16:14:02 +00:00
Timur Iskhodzhanov bd6cee7cc3 [ASan/Win tests] Add memcpy/strdup/strlen interception tests
llvm-svn: 208899
2014-05-15 16:02:56 +00:00
Alexander Kornienko 6262d2349c Fixed incorrect StringRef::find usage.
llvm-svn: 208898
2014-05-15 15:56:58 +00:00
NAKAMURA Takumi 2d35a06080 llvm/test/CodeGen/X86/combine-sse41-intrinsics.ll: Add explicit triple.
llvm-svn: 208897
2014-05-15 15:45:31 +00:00
Chandler Carruth 57e0ec7d20 Teach the compiler-rt custom compilation and linking CMake rules used
for sanitizers to pass the C++ compilation and exe linking flags through
from the host CMake configuration. We pass the target flags afterward,
allowing them to trump flags as needed. This is particularly important
when the flags direct Clang, even the just-built-Clang, toward the
standard library, linker, and other tools to use.

llvm-svn: 208896
2014-05-15 15:21:11 +00:00
Andrea Di Biagio d621120533 [X86] Teach the backend how to fold SSE4.1/AVX/AVX2 blend intrinsics.
Added target specific combine rules to fold blend intrinsics according
to the following rules:
 1) fold(blend A, A, Mask) -> A;
 2) fold(blend A, B, <allZeros>) -> A;
 3) fold(blend A, B, <allOnes>) -> B.

Added two new tests to verify that the new folding rules work for all
the optimized blend intrinsics.

llvm-svn: 208895
2014-05-15 15:18:15 +00:00
Zoran Jovanovic d6879febdc [mips][mips64r6] Add CLASS.fmt instructions
Differential Revision: http://reviews.llvm.org/D3712

llvm-svn: 208894
2014-05-15 15:16:36 +00:00
Timur Iskhodzhanov 5910d6d126 [ASan/Win tests] Add more DLL tests
llvm-svn: 208893
2014-05-15 15:13:06 +00:00
Zoran Jovanovic bdf1cd374f [mips][mips64r6] Add RINT.fmt instructions
Differential Revision: http://reviews.llvm.org/D3711

llvm-svn: 208892
2014-05-15 15:04:37 +00:00
Zoran Jovanovic 702d27e4db [mips][mips64r6] Add SELEQZ/SELNEZ.fmt instructions
Differential Revision: http://reviews.llvm.org/D3710

llvm-svn: 208891
2014-05-15 14:58:42 +00:00
Zoran Jovanovic 11d4ce1788 [mips][mips64r6] Add MAX/MIN/MAXA/MINA.fmt instructions
Differential Revision: http://reviews.llvm.org/D3709

llvm-svn: 208890
2014-05-15 14:54:06 +00:00
Timur Iskhodzhanov e23889692b [ASan/Win tests] Add more DLL tests: malloc & friends
llvm-svn: 208889
2014-05-15 14:42:41 +00:00
Tom Stellard 436780bebb R600/SI: Stop using VSrc_* as the default register class for types.
We now use SReg_* for integer types and VReg_* for floating-point types.
This should help simplify the SIFixSGPRCopies pass and no longer causes
ISel to insert a COPY after termiator instuctions that output a value.

This change is covered by exisitng tests.

llvm-svn: 208888
2014-05-15 14:41:57 +00:00
Tom Stellard a568738b47 R600/SI: Fix a bug with handling of INSERT_SUBREG in SIFixSGPRCopies
This prevents a future commit from regressing the load-i1.ll test.

llvm-svn: 208887
2014-05-15 14:41:55 +00:00
Tom Stellard 73b98ed8cf R600/SI: Only use SALU instructions for 64-bit add in a block of CF depth 0
llvm-svn: 208886
2014-05-15 14:41:54 +00:00
Tom Stellard 365a2b49f2 R600/SI: Use VALU instructions for i1 ops
llvm-svn: 208885
2014-05-15 14:41:50 +00:00
Timur Iskhodzhanov 3bd2c2fe90 [ASan/Win tests] Add the first DLL test
llvm-svn: 208884
2014-05-15 14:27:46 +00:00
Alexander Kornienko 23fe95904c Change the behavior of clang-tidy -checks=, remove -disable-checks.
Summary:
Make checks filtering more intuitive and easy to use. Remove
-disable-checks and change the format of -checks= to a comma-separated list of
globs with optional '-' prefix to denote exclusion. The -checks= option is now
cumulative, so it modifies defaults, not overrides them. Each glob adds or
removes to the current set of checks, so the filter can be refined or overriden
by adding globs.

Example:
  The default value for -checks= is
  '*,-clang-analyzer-alpha*,-llvm-include-order,-llvm-namespace-comment,-google-*',
  which allows all checks except for the ones named clang-analyzer-alpha* and
  others specified with the leading '-'. To allow all google-* checks one can
  write:
    clang-tidy -checks=google-* ...
  If one needs only google-* checks, we first need to remove everything (-*):
    clang-tidy -checks=-*,google-*
  etc.

I'm not sure if we need to change something here, so I didn't touch the docs
yet.

Reviewers: klimek, alexfh

Reviewed By: alexfh

Subscribers: cfe-commits

Differential Revision: http://reviews.llvm.org/D3770

llvm-svn: 208883
2014-05-15 14:27:36 +00:00
Daniel Jasper c0be7604cf clang-format: Fix Sphinx build error.
Patch by Adam Strzelecki, thank you!

llvm-svn: 208882
2014-05-15 13:55:19 +00:00
Timur Iskhodzhanov 130b5651d1 [ASan/Win tests] Add tests for malloc/calloc/realloc
llvm-svn: 208881
2014-05-15 13:50:12 +00:00
Tim Northover 60091cfeb9 TableGen: use correct MIOperand when printing aliases
Previously, TableGen assumed that every aliased operand consumed precisely 1
MachineInstr slot (this was reasonable because until a couple of days ago,
nothing more complicated was eligible for printing).

This allows a couple more ARM64 aliases to print so we can remove the special
code.

On the X86 side, I've gone for explicit AT&T size specifiers as the default, so
turned off a few of the aliases that would have just started printing.

llvm-svn: 208880
2014-05-15 13:36:01 +00:00
Alexander Musman cb7f9c40f8 C++11 - Use nullptr in lib/Sema/SemaOpenMP.cpp and some reformatting (no functional changes).
llvm-svn: 208879
2014-05-15 13:04:49 +00:00
Dmitry Vyukov 547089e2a5 tsan: allow to disable history collection
The mode is enabled with -DTSAN_NO_HISTORY=1 flag.
Intended mostly for research purposes (how fast can it go w/o history).

llvm-svn: 208878
2014-05-15 12:51:48 +00:00
Daniel Sanders e17212d621 [mips][mips64r6] Add bitswap, and dbitswap
Summary: Depends on D3728

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3729

llvm-svn: 208877
2014-05-15 12:18:23 +00:00
Jay Foad 5a29c367f7 Instead of littering asserts throughout the code after every call to
computeKnownBits, consolidate them into one assert at the end of
computeKnownBits itself.

llvm-svn: 208876
2014-05-15 12:12:55 +00:00
Tim Northover fb33438115 ARM64: update tests now that we print "mov" & "mvn".
llvm-svn: 208875
2014-05-15 12:11:10 +00:00
Tim Northover 2509a3fc64 ARM64: print correct aliases for NEON mov & mvn instructions
In all cases, if a "mov" alias exists, it is the canonical form of the
instruction. Now that TableGen can support aliases containing syntax variants,
we can enable them and improve the quality of the asm output.

llvm-svn: 208874
2014-05-15 12:11:02 +00:00
Timur Iskhodzhanov a357badc58 [ASan/Win tests] Add tests for stack array manipulation, as well as a use-after-return test
llvm-svn: 208873
2014-05-15 12:09:45 +00:00
Daniel Sanders 01124a0132 [mips][mips64r6] Add align and dalign
Summary: Depends on D3689

Reviewers: vmedic, zoran.jovanovic, jkolek

Reviewed By: jkolek

Differential Revision: http://reviews.llvm.org/D3728

llvm-svn: 208872
2014-05-15 12:06:36 +00:00
Timur Iskhodzhanov 2dbedf5e93 [ASan/Win tests] Add tests for operator new/new[]/delete/delete[]
llvm-svn: 208871
2014-05-15 11:55:40 +00:00
Alp Toker 281dfe85d3 Fix typo 'fourty' in tests
llvm-svn: 208870
2014-05-15 11:33:29 +00:00
Alp Toker f03763a44b Fix typos
llvm-svn: 208869
2014-05-15 11:27:39 +00:00
Tim Northover 0f9355b3b0 AArch64: update test after LLVM CodeGen change
llvm-svn: 208868
2014-05-15 11:21:39 +00:00
Tim Northover d8d65a69cf TableGen/ARM64: print aliases even if they have syntax variants.
To get at least one use of the change (and some actual tests) in with its
commit, I've enabled the AArch64 & ARM64 NEON mov aliases.

llvm-svn: 208867
2014-05-15 11:16:32 +00:00
Tim Northover dd8fca5136 ARM64: add correct vector registers during asm parsing
Previously, we ignored the difference between V64 and V128 when parsing
assembly: they both got mapped to registers in the FPR128 class. This is
basically harmless at the moment because they both print and encode the same
way. However, it will affect the printing of aliases.

llvm-svn: 208866
2014-05-15 11:16:19 +00:00
Timur Iskhodzhanov dd2d84a223 [ASan/Win tests] Add tests for downcast-related overflows, as well as CRT initiazliers
llvm-svn: 208865
2014-05-15 11:14:00 +00:00
Bradley Smith 5c44b08912 [ARM64] Improve load/store diagnostics and forbid 32-bit register addresses
llvm-svn: 208864
2014-05-15 11:08:30 +00:00
Bradley Smith e0483f9cd1 [ARM64] Parse fixed vector lanes properly so that diagnostics can be emitted
llvm-svn: 208863
2014-05-15 11:07:57 +00:00
Bradley Smith c294914adc [ARM64] Add/Fixup diagnostics for floating point immediates
llvm-svn: 208862
2014-05-15 11:07:28 +00:00
Bradley Smith 3d1a9ef162 [ARM64] Add condition code operand type such that proper diagnostics can be emitted
llvm-svn: 208861
2014-05-15 11:06:51 +00:00
Bradley Smith 13a76e5b88 [ARM64] Add more simple diagnostics for immediate/shift ranges
llvm-svn: 208860
2014-05-15 11:06:16 +00:00
Timur Iskhodzhanov f32b690f69 [ASan/Win tests] Add tests for aligned mallocs, bitfields and global strings
llvm-svn: 208859
2014-05-15 10:58:35 +00:00
Daniel Sanders b59e1a41f4 [mips][mips64r6] Add addiupc, aluipc, and auipc
Summary:
No support for symbols in place of the immediate yet since it requires new
relocations.

Depends on D3671

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3689

llvm-svn: 208858
2014-05-15 10:45:58 +00:00
Daniel Sanders a3412b13d4 [mips][mips64r6] Add aui, daui, dahi, and dati
Summary: Depends on D3671

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3759

llvm-svn: 208857
2014-05-15 10:27:19 +00:00
Chandler Carruth a0e5695ad9 Teach the constant folder to look through bitcast constant expressions
much more effectively when trying to constant fold a load of a constant.
Previously, we only handled bitcasts by trying to find a totally generic
byte representation of the constant and use that. Now, we look through
the bitcast to see what constant we might fold the load into, and then
try to form a constant expression cast of the found value that would be
equivalent to loading the value.

You might wonder why on earth this actually matters. Well, turns out
that the Itanium ABI causes us to create a single array for a vtable
where the first elements are virtual base offsets, followed by the
virtual function pointers. Because the array is homogenous the element
type is consistently i8* and we inttoptr the virtual base offsets into
the initial elements.

Then constructors bitcast these pointers to i64 pointers prior to
loading them. Boom, no more constant folding of virtual base offsets.
This is the first fix to LLVM to address the *insane* performance Eric
Niebler discovered with Clang on his range comprehensions[1]. There is
more to come though, this doesn't *really* fix the problem fully.

[1]: http://ericniebler.com/2014/04/27/range-comprehensions/

llvm-svn: 208856
2014-05-15 09:56:28 +00:00
Daniel Sanders 19627f470b [mips][mips64r6] Test that branch likelies are not accepted on MIPS64r6.
Summary:
They aren't implemented for any ISA at the moment.

Depends on D3670

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3671

llvm-svn: 208855
2014-05-15 09:47:43 +00:00