llvm-project

Commit Graph

Author	SHA1	Message	Date
Sam Parker	3fa0ccffc6	[AArch64] Add V8_2aOps feature to Cortex-A55 and 75 Add the missing hardware features the ProcA55 and ProcA75 feature. These are already enabled via the target parser, but I had missed them in the backend. Differential Revision: https://reviews.llvm.org/D37974 llvm-svn: 313535	2017-09-18 14:46:14 +00:00
Ahmed Bougacha	a1991bdde2	[AArch64] armv8-A doesn't have CRC. That's only a required extension as of v8.1a. Remove it from the "generic" CPU as well: it should only support the base ISA (and binutils agrees). Also unify the MC tests into crc.s and arm64-crc32.s llvm-svn: 302077	2017-05-03 20:33:52 +00:00

Author

SHA1

Message

Date

Sam Parker

3fa0ccffc6

[AArch64] Add V8_2aOps feature to Cortex-A55 and 75

Add the missing hardware features the ProcA55 and ProcA75 feature.
These are already enabled via the target parser, but I had missed
them in the backend.

Differential Revision: https://reviews.llvm.org/D37974

llvm-svn: 313535

2017-09-18 14:46:14 +00:00

Ahmed Bougacha

a1991bdde2

[AArch64] armv8-A doesn't have CRC.

That's only a required extension as of v8.1a.

Remove it from the "generic" CPU as well: it should only support the
base ISA (and binutils agrees).

Also unify the MC tests into crc.s and arm64-crc32.s

llvm-svn: 302077

2017-05-03 20:33:52 +00:00

2 Commits