Commit Graph

2 Commits

Author SHA1 Message Date
Sander de Smalen e64206a02c [AArch64][SVE] Asm: Enable instructions to be prefixed.
This patch enables instructions that are destructive on their
destination- and first source operand, to be prefixed with a
MOVPRFX instruction.

This patch also adds a variety of tests:

- positive tests for all instructions and forms that accept a
  movprfx for either or both predicated and unpredicated forms.

- negative tests for all instructions and forms that do not accept
  an unpredicated or predicated movprfx.

- negative tests for the diagnostics that get emitted when a MOVPRFX
  instruction is used incorrectly.

This is patch [2/2] in a series to add MOVPRFX instructions:
- Patch [1/2]: https://reviews.llvm.org/D49592
- Patch [2/2]: https://reviews.llvm.org/D49593

Reviewers: rengolin, SjoerdMeijer, samparker, fhahn, javed.absar

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D49593

llvm-svn: 338261
2018-07-30 16:05:45 +00:00
Sander de Smalen fcb636d222 [AArch64][SVE] Asm: Predicated floating point reductions.
This patch adds support for various floating-point
reduction operations:

  FADDA    strictly-ordered add reduction, accumulating in scalar
  FADDV    recursive add reduction to scalar
  FMAXV    recursive max reduction to scalar
  FMINV    recursive min reduction to scalar
  FMAXNMV  recursive max number reduction to scalar
  FMINNMV  recursive min number reduction to scalar

The reduction is predicated, e.g.

  fadda d0, p0, d0, z1.d

performs the add-reduction in strict order on active elements
in z1, accumulating into d0.

  faddv d0, p0, z1.d

performs the add-reduction (not in strict order)
on active elements in z1, storing the result in d0.

llvm-svn: 338123
2018-07-27 13:58:48 +00:00