Commit Graph

11 Commits

Author SHA1 Message Date
David Blaikie a79ac14fa6 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

llvm-svn: 230794
2015-02-27 21:17:42 +00:00
Vladimir Medic 187958b27a Replace obsolete -mattr=n64 command line option with -target-abi=n64. No functional changes.
llvm-svn: 230628
2015-02-26 12:29:48 +00:00
Daniel Sanders 8bb4c858bc [mips][mips64r6] Improve tests affected by the changes to multiplies and divides
Summary:
MIPS32r6/MIPS64r6 support has not been added yet.

inlineasm-cnstrnt-reg.ll:
  Explicitly specify the CPU since it will not work on MIPS32r6/MIPS64r6
  when -integrated-as is the default. We can't change the mnemonic since the
  LO register is an implicit def of mtlo and MIPS32r6/MIPS64r6 has no
  instructions that use LO.

2008-08-01-AsmInline.ll:
  Explicitly specify the CPU since MIPS32r6/MIPS64r6 will correctly emit
  different code and this is a regression test.

mips64instrs.ll and mips64muldiv.ll
  Check registers and the way the multiply is used in m1

divrem.ll
  Check registers and use multiple filecheck prefixes to limit redundancy

Reviewers: vmedic, jkolek, zoran.jovanovic, matheusalmeida

Reviewed By: matheusalmeida

Subscribers: matheusalmeida

Differential Revision: http://reviews.llvm.org/D3894

llvm-svn: 210656
2014-06-11 15:48:00 +00:00
Akira Hatanaka 7473b4705a [mips] Properly parse registers that appear in inline-asm constraints.
llvm-svn: 188336
2013-08-14 00:21:25 +00:00
Akira Hatanaka c669d7a6db Have getRegForInlineAsmConstraint return the correct register class when target
is Mips64.

llvm-svn: 147516
2012-01-04 02:45:01 +00:00
Akira Hatanaka bbc5555bee Fix test cases to use FileCheck.
llvm-svn: 145716
2011-12-02 22:28:09 +00:00
Duncan Sands 68c30907cc Correct bogus module triple specifications.
llvm-svn: 112469
2010-08-30 10:48:29 +00:00
Dan Gohman c8054d90fb Eliminate more uses of llvm-as and llvm-dis.
llvm-svn: 81293
2009-09-09 00:09:15 +00:00
Dan Gohman 0d4bbf2c4a Remove obsolete -f flags.
llvm-svn: 79992
2009-08-25 15:38:29 +00:00
Duncan Sands 8475d56794 Turn on LegalizeTypes, the new type legalization
codegen infrastructure, by default.  Please report
any breakage to the mailing lists.

llvm-svn: 58232
2008-10-27 08:42:46 +00:00
Bruno Cardoso Lopes 9c8b9d4606 Batch 5 of Mips CodeGen tests
llvm-svn: 54510
2008-08-08 04:09:57 +00:00