Commit Graph

328663 Commits

Author SHA1 Message Date
Richard Smith 8d2eaf9239 PR43547: substitute into the type of a non-type template parameter if
it's instantiation-dependent, even if it's not dependent.

There might be a SFINAE check in the parameter type.

llvm-svn: 373643
2019-10-03 18:24:40 +00:00
Vitaly Buka 6fb03a290b [compiler-rt] More optimization levels in signal_line.cpp test
llvm-svn: 373642
2019-10-03 18:18:35 +00:00
Simon Pilgrim eb8d85e5db [X86] matchShuffleWithSHUFPD - use Zeroable element mask directly. NFCI.
We can make use of the Zeroable mask to indicate which elements we can safely set to zero instead of creating a target shuffle mask on the fly.

This only leaves one user of createTargetShuffleMask which we can hopefully get rid of in a similar manner.

This is part of the work to fix PR43024 and allow us to use SimplifyDemandedElts to simplify shuffle chains - we need to get to a point where the target shuffle masks isn't adjusted by its source inputs in setTargetShuffleZeroElements but instead we cache them in a parallel Zeroable mask.

llvm-svn: 373641
2019-10-03 18:13:50 +00:00
Jonas Devlieghere 085baf8d4e [dsymutil] Don't overload LinkOptions.
This should fix the build bots:

  error: declaration of ‘llvm::dsymutil::LinkOptions
  DsymutilOptions::LinkOptions’ [-fpermissive]

llvm-svn: 373640
2019-10-03 18:02:09 +00:00
Matt Arsenault ed77b27441 AMDGPU/GlobalISel: Handle RegBankSelect of G_INSERT_VECTOR_ELT
llvm-svn: 373639
2019-10-03 17:59:03 +00:00
Matt Arsenault 233ff982c7 AMDGPU/GlobalISel: Split 64-bit vector extracts during RegBankSelect
Register indexing 64-bit elements is possible on the SALU, but not the
VALU. Handle splitting this into two 32-bit indexes. Extend waterfall
loop handling to allow moving a range of instructions.

llvm-svn: 373638
2019-10-03 17:55:27 +00:00
Matt Arsenault 56271fe180 AMDGPU/GlobalISel: Allow VGPR to index SGPR register
We can still do a waterfall loop over the index if using a VGPR to
index an SGPR. The result will still be a VGPR, but we can avoid the
wide copy of the source register to a VGPR.

llvm-svn: 373637
2019-10-03 17:50:32 +00:00
Matt Arsenault 9256183994 AMDGPU/GlobalISel: Add some more tests for G_INSERT legalization
llvm-svn: 373636
2019-10-03 17:50:31 +00:00
Matt Arsenault 3d23e58dbe AMDGPU/GlobalISel: Fix mutationIsSane assert v8s8 and
This would try to do FewerElements to v9s8

llvm-svn: 373635
2019-10-03 17:50:29 +00:00
Michael Liao 691e44c146 [HIP] Enable specifying different default gpu arch for HIP/CUDA.
Reviewers: tra, yaxunl

Subscribers: cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D68394

llvm-svn: 373634
2019-10-03 17:49:20 +00:00
Michael Liao 9c1503f669 Fix build failure with GCC on identifier reusing.
- GCC is different from clang and other compilers on that.
  https://godbolt.org/z/CeQE1V

llvm-svn: 373633
2019-10-03 17:47:46 +00:00
Vitaly Buka 1fff2881a8 compiler-rt: move all __GLIBC_PREREQ into own header file
Reviewers: eugenis

Subscribers: dberris, #sanitizers, llvm-commits

Tags: #sanitizers, #llvm

Differential Revision: https://reviews.llvm.org/D68177

llvm-svn: 373632
2019-10-03 17:46:07 +00:00
Louis Dionne c5b74bf6e5 [libc++] Add a per-target flag to include the generated config_site
This allows propagating the include automatically to targets that
depend on one of the libc++ targets such as the benchmarks. Note
that the GoogleBenchmark build itself still needs to manually specify
the -include, since I don't know of any way to have an external project
link against one of the libc++ targets (which would propagate the -include
automatically).

llvm-svn: 373631
2019-10-03 17:20:50 +00:00
Tom Stellard e6f5171305 AMDGPU/SILoadStoreOptimizer: Optimize scanning for mergeable instructions
Summary:
This adds a pre-pass to this optimization that scans through the basic
block and generates lists of mergeable instructions with one list per unique
address.

In the optimization phase instead of scanning through the basic block for mergeable
instructions, we now iterate over the lists generated by the pre-pass.

The decision to re-optimize a block is now made per list, so if we fail to merge any
instructions with the same address, then we do not attempt to optimize them in
future passes over the block.  This will help to reduce the time this pass
spends re-optimizing instructions.

In one pathological test case, this change reduces the time spent in the
SILoadStoreOptimizer from 0.2s to 0.03s.

This restructuring will also make it possible to implement further solutions in
this pass, because we can now add less expensive checks to the pre-pass and
filter instructions out early which will avoid the need to do the expensive
scanning during the optimization pass. For example, checking for adjacent
offsets is an inexpensive test we can move to the pre-pass.

Reviewers: arsenm, pendingchaos, rampitec, nhaehnle, vpykhtin

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65961

llvm-svn: 373630
2019-10-03 17:11:47 +00:00
James Molloy 9972c992eb [ModuloSchedule] removeBranch() *before* creating the trip count condition
The Hexagon code assumes there's no existing terminator when inserting its
trip count condition check.

This causes swp-stages5.ll to break. The generated code looks good to me,
it is likely a permutation. I have disabled the new codegen path to keep
everything green and will investigate along with the other 3-4 tests
that have different codegen.

Fixes expensive-checks build.

llvm-svn: 373629
2019-10-03 17:10:32 +00:00
John Brawn b44204c77e [libunwind] Adjust libunwind_01.pass.cpp test for ARM EHABI
ARM EHABI unwinding tables only store the start address of each function, so the
last function is assumed to cover the entire address space after it. The test
picks an address on the stack assuming that it's in no function, but because of
the above it's actually resolved to the last function. Fix this by using address
0 instead.

Differential Revision: https://reviews.llvm.org/D68387

llvm-svn: 373628
2019-10-03 17:01:04 +00:00
Nico Weber b01ebd6c1d gn build: (manually) merge r373622
llvm-svn: 373627
2019-10-03 16:59:12 +00:00
Simon Pilgrim 86976c91cf DeclBase/DeclCXX/DeclTemplate - silence static analyzer getAs<> null dereference warnings. NFCI.
The static analyzer is warning about potential null dereferences, but in these cases we should be able to use castAs<> directly and if not assert will fire for us.

llvm-svn: 373626
2019-10-03 16:58:01 +00:00
Louis Dionne 0961a152d8 [libc++] Add missing revision number in ABI changelog
llvm-svn: 373625
2019-10-03 16:50:05 +00:00
Alexey Bataev 36724b78e8 [OPENMP]Fix emission of the declare target variables in device mode.
Declare target variables must be emitted in device mode, target triples
can be empty in this case.

llvm-svn: 373624
2019-10-03 16:46:49 +00:00
Jonas Devlieghere 2733bde663 [dsymutil] Improve consistency by removing redundant namespaces (NFC)
The dsymutil implementation file has a using-directive for the llvm
namespace. This patch just removes redundant namespace qualifiers.

llvm-svn: 373623
2019-10-03 16:34:44 +00:00
Jonas Devlieghere eddc1a4e95 [dsymutil] Tablegenify option parsing
This patch reimplements command line option parsing in dsymutil with
Tablegen and libOption. The main motivation for this change is to
prevent clashes with other cl::opt options defined in llvm. Although
it's a bit more heavyweight, it has some nice advantages such as no
global static initializers and better separation between the code and
the option definitions.

I also used this opportunity to improve how dsymutil deals with
incompatible options. Instead of having checks spread across the code,
everything is now grouped together in verifyOptions. The fact that the
options are no longer global means that we need to pass them around a
bit more, but I think it's worth the trade-off.

Differential revision: https://reviews.llvm.org/D68361

llvm-svn: 373622
2019-10-03 16:34:41 +00:00
Yonghong Song 02ac75092d [BPF] Handle offset reloc endpoint ending in the middle of chain properly
During studying support for bitfield, I found an issue for
an example like the one in test offset-reloc-middle-chain.ll.
  struct t1 { int c; };
  struct s1 { struct t1 b; };
  struct r1 { struct s1 a; };
  #define _(x) __builtin_preserve_access_index(x)
  void test1(void *p1, void *p2, void *p3);
  void test(struct r1 *arg) {
    struct s1 *ps = _(&arg->a);
    struct t1 *pt = _(&arg->a.b);
    int *pi = _(&arg->a.b.c);
    test1(ps, pt, pi);
  }

The IR looks like:
  %0 = llvm.preserve.struct.access(base, ...)
  %1 = llvm.preserve.struct.access(%0, ...)
  %2 = llvm.preserve.struct.access(%1, ...)
  using %0, %1 and %2

In this case, we need to generate three relocatiions
corresponding to chains: (%0), (%0, %1) and (%0, %1, %2).
After collecting all the chains, the current implementation
process each chain (in a map) with code generation sequentially.
For example, after (%0) is processed, the code may look like:
  %0 = base + special_global_variable
  // llvm.preserve.struct.access(base, ...) is delisted
  // from the instruction stream.
  %1 = llvm.preserve.struct.access(%0, ...)
  %2 = llvm.preserve.struct.access(%1, ...)
  using %0, %1 and %2

When processing chain (%0, %1), the current implementation
tries to visit intrinsic llvm.preserve.struct.access(base, ...)
to get some of its properties and this caused segfault.

This patch fixed the issue by remembering all necessary
information (kind, metadata, access_index, base) during
analysis phase, so in code generation phase there is
no need to examine the intrinsic call instructions.
This also simplifies the code.

Differential Revision: https://reviews.llvm.org/D68389

llvm-svn: 373621
2019-10-03 16:30:29 +00:00
Alexey Bataev ba643691dd [OPENMP]Improve diagnostics for not found declare target entries.
We can point to the target region + emit parent functions names/real var
names if they were not found in host module during device codegen.

llvm-svn: 373620
2019-10-03 16:20:34 +00:00
Guillaume Chatelet d1f23bd225 Revert "[Alignment][NFC] Allow constexpr Align"
This reverts commit b3af236fb5.

llvm-svn: 373619
2019-10-03 15:53:50 +00:00
Edward Jones f5177a7db4 [RISCV] Add obsolete aliases of fscsr, frcsr (fssr, frsr)
These old aliases were renamed, but are still used by some projects (eg newlib).

Differential Revision: https://reviews.llvm.org/D68392

llvm-svn: 373618
2019-10-03 15:47:28 +00:00
David Bolvansky e83309e02a [NFC] Added missing changes for rL373614
llvm-svn: 373616
2019-10-03 15:26:26 +00:00
David Bolvansky b4ee523ffc [Diagnostics] Bitwise negation of a boolean expr always evaluates to true; warn with -Wbool-operation
Requested here:
http://lists.llvm.org/pipermail/cfe-dev/2019-October/063452.html

llvm-svn: 373614
2019-10-03 15:17:59 +00:00
Simon Pilgrim 1fae74480b Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.
llvm-svn: 373613
2019-10-03 15:10:47 +00:00
Simon Pilgrim c15b38ec7d ExprConstant - silence static analyzer getAs<> null dereference warnings. NFCI.
The static analyzer is warning about potential null dereferences, but in these cases we should be able to use castAs<> directly and if not assert will fire for us.

llvm-svn: 373612
2019-10-03 15:08:30 +00:00
Simon Pilgrim d834f1f63e Remove duplicate P->getAs<PointerType>() call. NFCI.
llvm-svn: 373611
2019-10-03 15:08:20 +00:00
George Rimar c18585e32e [yaml2obj] - Add a Size tag support for SHT_LLVM_ADDRSIG sections.
It allows using "Size" with or without "Content" in YAML descriptions of
SHT_LLVM_ADDRSIG sections.

Differential revision: https://reviews.llvm.org/D68334

llvm-svn: 373610
2019-10-03 15:02:18 +00:00
Sumanth Gundapaneni 069cb6282d Test commit.
llvm-svn: 373609
2019-10-03 14:57:49 +00:00
Sanjay Patel 38c265fe26 [MSP430] add tests for unwanted shift codegen; NFC (PR43542)
llvm-svn: 373607
2019-10-03 14:54:03 +00:00
George Rimar fc9104d42a Recommit r373598 "[yaml2obj/obj2yaml] - Add support for SHT_LLVM_ADDRSIG sections."
Fix: call `consumeError()` for a case missed.

Original commit message:

SHT_LLVM_ADDRSIG is described here:
https://llvm.org/docs/Extensions.html#sht-llvm-addrsig-section-address-significance-table

This patch teaches tools to dump them and to parse the YAML declarations of such sections.

Differential revision: https://reviews.llvm.org/D68333

llvm-svn: 373606
2019-10-03 14:52:33 +00:00
Sanjay Patel 2c9c7d6809 [UpdateTestChecks] add basic support for parsing msp430 asm
llvm-svn: 373605
2019-10-03 14:34:28 +00:00
GN Sync Bot d1a4b82274 gn build: Merge r373601
llvm-svn: 373603
2019-10-03 14:28:27 +00:00
Louis Dionne 6f9459f7fe [libc++abi] Do not export some implementation-detail functions
Summary:
Those functions started being mistakenly exported from the libc++abi
shared library after commit r344152 in 2018. Removing these symbols is
technically an ABI break. However, they are not part of the C++ ABI,
they haven't ever been re-exported from libc++, and they are not
declared in any public header, so it's very unlikely that calls to
these functions exist out there. Also, the functions have reserved
names, so any impacted user would have to have tried really hard
being broken by this removal.

Note that avoiding this kind of problem is exactly why we're now
controlling exported symbols explicitly with a textual list.

Also note that applying the hidden visibility attribute is necessary
because the list of exported symbols is only used on Apple platforms
for the time being.

Reviewers: phosek, mclow.lists, EricWF

Subscribers: christof, jkorous, dexonsmith, libcxx-commits

Tags: #libc

Differential Revision: https://reviews.llvm.org/D68357

llvm-svn: 373602
2019-10-03 14:24:53 +00:00
Bardia Mahjour f6c34de117 [PGO] Refactor Value Profiling into a plugin based oracle and create a well defined API for the plugins.
Summary: This PR creates a utility class called ValueProfileCollector that tells PGOInstrumentationGen and PGOInstrumentationUse what to value-profile and where to attach the profile metadata. It then refactors logic scattered in PGOInstrumentation.cpp into two plugins that plug into the ValueProfileCollector.

Authored By: Wael Yehia <wyehia@ca.ibm.com>

Reviewer: davidxl, tejohnson, xur

Reviewed By: davidxl, tejohnson, xur

Subscribers: llvm-commits

Tag: #llvm

Differential Revision: https://reviews.llvm.org/D67920

Patch By Wael Yehia <wyehia@ca.ibm.com>

llvm-svn: 373601
2019-10-03 14:20:50 +00:00
Ehsan Amiri f21dbcca90 [AArch64][SVE] Adding patterns for floating point SVE add instructions.
llvm-svn: 373600
2019-10-03 14:19:55 +00:00
George Rimar 9f6cf2a081 Revert r373598 "[yaml2obj/obj2yaml] - Add support for SHT_LLVM_ADDRSIG sections."
It broke BB:
http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/18655/steps/test/logs/stdio

llvm-svn: 373599
2019-10-03 14:04:47 +00:00
George Rimar 32cbabfecb [yaml2obj/obj2yaml] - Add support for SHT_LLVM_ADDRSIG sections.
SHT_LLVM_ADDRSIG is described here:
https://llvm.org/docs/Extensions.html#sht-llvm-addrsig-section-address-significance-table

This patch teaches tools to dump them and to parse the YAML declarations of such sections.

Differential revision: https://reviews.llvm.org/D68333

llvm-svn: 373598
2019-10-03 13:57:08 +00:00
Roman Lebedev c780645736 [NFC][InstCombine] Some tests for sub-of-negatible pattern
As we have previously estabilished, `sub` is an outcast,
and should be considered non-canonical iff it can be converted to `add`.

It can be converted to `add` if it's second operand can be negated.
So far we mostly only do that for constants and negation itself,
but we should be more through.

llvm-svn: 373597
2019-10-03 13:36:00 +00:00
Djordje Todorovic de6b59cd20 [llvm-locstats] Copy the script only when needed; NFC
llvm-svn: 373596
2019-10-03 13:18:14 +00:00
Guillaume Chatelet d400d45150 [Alignment][NFC] Remove StoreInst::setAlignment(unsigned)
Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet, bollu, jdoerfert

Subscribers: hiraditya, asbirlea, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D68268

llvm-svn: 373595
2019-10-03 13:17:21 +00:00
George Rimar 6079498c51 [llvm-readobj] - Stop using a precompiled binary in all.test
Having a precompiled binary here is excessive.
I also added a few missing tags.

Differential revision: https://reviews.llvm.org/D68386

llvm-svn: 373594
2019-10-03 13:13:23 +00:00
Yitzhak Mandelbaum e80e889695 [libTooling] Add various Stencil combinators for expressions.
Summary:
This revision adds three new Stencil combinators:
* `expression`, which idiomatically constructs the source for an expression,
  including wrapping the expression's source in parentheses if needed.
* `deref`, which constructs an idiomatic dereferencing expression.
* `addressOf`, which constructs an idiomatic address-taking expression.

Reviewers: gribozavr

Subscribers: cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D68315

llvm-svn: 373593
2019-10-03 13:01:00 +00:00
Guillaume Chatelet c79099e0f4 [Alignment][Clang][NFC] Add CharUnits::getAsAlign
Summary:
This is a prerequisite to removing `llvm::GlobalObject::setAlignment(unsigned)`.
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: jholewinski, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D68274

llvm-svn: 373592
2019-10-03 13:00:29 +00:00
Simon Atanasyan f6551ddfce [mips] Push `fixup_Mips_LO16` fixup for `jialc` and `jic` instructions
llvm-svn: 373591
2019-10-03 12:08:26 +00:00
Simon Atanasyan bf333421da [llvm-readobj][mips] Remove non-standard --misp-xxx flags
llvm-readobj "non-standard" flags `--mips-plt-got`, `--mips-abi-flags`,
`--mips-reginfo`, and `--mips-options` are superseded by the `--arch-specific`
flag and can be removed now.

llvm-svn: 373590
2019-10-03 12:08:11 +00:00