llvm-project

Commit Graph

Author	SHA1	Message	Date
Stanislav Mekhanoshin	277de43d88	[AMDGPU] Unify intrinsic ret/nortn interface We have a single noret intrinsic an a lot of special handling around it. Declare it just as any other but do not define rtn instructions itself instead. Differential Revision: https://reviews.llvm.org/D87719	2020-09-15 15:26:42 -07:00
Matt Arsenault	e1a2f4713c	AMDGPU: Match global saddr addressing mode The previous implementation was incorrect, and based off incorrect instruction definitions. Unfortunately we can't match natural addressing in a lot of cases due to the shift/scale applied in getelementptrs. This relies on reducing the 64-bit shift to 32-bits.	2020-08-17 15:28:14 -04:00
Matt Arsenault	087dcbe9bc	AMDGPU: Add baseline tests for global saddr matching	2020-08-17 15:23:13 -04:00

Author

SHA1

Message

Date

Stanislav Mekhanoshin

277de43d88

[AMDGPU] Unify intrinsic ret/nortn interface

We have a single noret intrinsic an a lot of special handling
around it. Declare it just as any other but do not define rtn
instructions itself instead.

Differential Revision: https://reviews.llvm.org/D87719

2020-09-15 15:26:42 -07:00

Matt Arsenault

e1a2f4713c

AMDGPU: Match global saddr addressing mode

The previous implementation was incorrect, and based off incorrect
instruction definitions. Unfortunately we can't match natural
addressing in a lot of cases due to the shift/scale applied in
getelementptrs. This relies on reducing the 64-bit shift to 32-bits.

2020-08-17 15:28:14 -04:00

Matt Arsenault

087dcbe9bc

AMDGPU: Add baseline tests for global saddr matching

2020-08-17 15:23:13 -04:00

3 Commits