4 Commits

Author	SHA1	Message	Date
Jinsong Ji	9fd81dc139	[PowerPC] Use xxleqv to set all one vector IMM(-1). ... Summary: xxspltib/vspltisb are 3 cycle PM instructions, xxleqv is 2 cycle ALU instruction. We should use xxleqv to set all one vectors. Reviewers: hfinkel, nemanjai, steven.zhang Subscribers: hiraditya, kbarton, MaskRay, shchenz, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65529 llvm-svn: 369006	2019-08-15 14:32:51 +00:00
Nemanja Ivanovic	ef4a3aa549	[PowerPC] Exploit the vector min/max instructions ... Use the PPC vector min/max instructions for computing the corresponding operation as these should be faster than the compare/select sequences we currently emit. Differential revision: https://reviews.llvm.org/D47332 llvm-svn: 362759	2019-06-06 23:49:01 +00:00
Sanjay Patel	84ceae6048	[CGP] adjust target constraints for forming uaddo ... There are 2 changes visible here: 1. There's no reason to limit this transform based on number of condition registers. That diff allows PPC to produce slightly better (dot-instructions should be generally good) code. Note: someone that cares about PPC codegen might want to look closer at that output because it seems like we could still improve this. 2. We (probably?) should not bother trying to form uaddo (or other overflow ops) when there's no target support for such an op. This goes beyond checking whether the op is expanded because both PPC and AArch64 show better codegen for standard types regardless of whether the op is legal/custom. llvm-svn: 353001	2019-02-03 17:53:09 +00:00
Sanjay Patel	359a97310b	[PowerPC] add tests for saturating add; NFC ... This is copied from the existing test files for x86/AArch. llvm-svn: 352987	2019-02-03 12:42:54 +00:00