a8d63dc289
[Hexagon] Split all selection patterns into a separate file
...
This is just the basic separation, without any cleanup. Further changes
will follow.
llvm-svn: 286036
2016-11-05 15:01:38 +00:00
654dc11b79
[Hexagon] Rename operand/predicate names for unshifted integers
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For example, rename s6Ext to s6_0Ext. The names for shifted integers
include the underscore and this will make the naming consistent. It
also exposed a few duplicates that were removed.
llvm-svn: 285728
2016-11-01 19:02:10 +00:00
046da74699
[Hexagon] Do not expand ISD::SELECT for HVX vectors
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llvm-svn: 285297
2016-10-27 14:30:16 +00:00
eabc0d0fd5
[Hexagon] Clean up some miscellaneous V60 intrinsics a bit
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llvm-svn: 278823
2016-08-16 17:14:44 +00:00
17aa4136a2
[Hexagon] Standardize vector predicate load/store pseudo instructions
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- Remove unused instructions: LDriq_pred_vec_V6, STriq_pred_vec_V6, and
the 128B counterparts.
- Rename:
LDriq_pred_V6 PS_vloadrq_ai
LDriq_pred_V6_128B PS_vloadrq_ai_128B
STriq_pred_V6 PS_vstorerq_ai
STriq_pred_V6_128B PS_vstorerq_ai_128B
llvm-svn: 278813
2016-08-16 15:43:54 +00:00
f285963608
[Hexagon] Cleanup and standardize vector load/store pseudo instructions
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Remove the following single-vector load/store pseudo instructions, use real
instructions instead:
LDriv_pseudo_V6 STriv_pseudo_V6
LDriv_pseudo_V6_128B STriv_pseudo_V6_128B
LDrivv_indexed STrivv_indexed
LDrivv_indexed_128B STrivv_indexed_128B
Rename the double-vector load/store pseudo instructions, add unaligned
counterparts:
-- old -- -- new -- -- unaligned --
LDrivv_pseudo_V6 PS_vloadrw_io PS_vloadrwu_io
LDrivv_pseudo_V6_128B PS_vloadrw_io_128B PS_vloadrwu_io_128B
STrivv_pseudo_V6 PS_vstorerw_io PS_vstorerwu_io
STrivv_pseudo_V6_128B PS_vstorerw_io_128 PS_vstorerwu_io_128
llvm-svn: 278564
2016-08-12 21:05:05 +00:00
258af19d99
[Hexagon] Standardize "select" pseudo-instructions
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- PS_pselect: general register pairs
- PS_vselect: vector registers (+ 128B version)
- PS_wselect: vector register pairs (+ 128B version)
llvm-svn: 278390
2016-08-11 19:12:18 +00:00
0bd55a7608
[Hexagon] Custom lower VECTOR_SHUFFLE and EXTRACT_SUBVECTOR for HVX
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If the mask of a vector shuffle has alternating odd or even numbers
starting with 1 or 0 respectively up to the largest possible index
for the given type in the given HVX mode (single of double) we can
generate vpacko or vpacke instruction respectively.
E.g.
%42 = shufflevector <32 x i16> %37, <32 x i16> %41,
<32 x i32> <i32 1, i32 3, ..., i32 63>
is %42.h = vpacko(%41.w, %37.w)
Patch by Pranav Bhandarkar.
llvm-svn: 277168
2016-07-29 16:44:27 +00:00
2a480599bb
[Hexagon] Post-increment loads/stores enhancements
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- Generate vector post-increment stores more aggressively.
- Predicate post-increment and vector stores in early if-conversion.
llvm-svn: 276800
2016-07-26 20:30:30 +00:00
2d65ea74dc
[Hexagon] Improve handling of unaligned vector loads and stores
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llvm-svn: 264584
2016-03-28 15:43:03 +00:00
c168c0165c
[Hexagon] Implement CONCAT_VECTORS for HVX using V6_vcombine
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llvm-svn: 254617
2015-12-03 16:47:20 +00:00
195dc8d0db
[Hexagon] HVX vector register classes and more isel patterns
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llvm-svn: 254132
2015-11-26 04:33:11 +00:00
7c9587136d
[Hexagon] Adding skeleton of HVX extension instructions.
...
llvm-svn: 250600
2015-10-17 01:33:04 +00:00
Krzysztof Parzyszek