Evan Cheng
184ec26fcd
Enable predication of NEON instructions in Thumb2 mode.
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llvm-svn: 89748
2009-11-24 08:06:15 +00:00
Evan Cheng
a33fc86be3
Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td.
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llvm-svn: 89542
2009-11-21 06:21:52 +00:00
Evan Cheng
bbd50b0f78
Also CSE non-pic load from constant pools.
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llvm-svn: 89440
2009-11-20 02:10:27 +00:00
Bob Wilson
290e9a47a9
Add a target hook to allow changing the tail duplication limit based on the
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contents of the block to be duplicated. Use this for ARM Cortex A8/9 to
be more aggressive tail duplicating indirect branches, since it makes it
much more likely that they will be predicted in the branch target buffer.
Testcase coming soon.
llvm-svn: 89187
2009-11-18 03:34:27 +00:00
Jim Grosbach
01c1cae34d
Detect need for autoalignment of the stack earlier to catch spills more
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conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling
llvm-svn: 88874
2009-11-15 21:45:34 +00:00
Jim Grosbach
74ae3e5b0e
set the def of the VLD1q64 properly
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llvm-svn: 88873
2009-11-15 21:05:07 +00:00
Evan Cheng
6ad7da96fe
- Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.
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- If destination is a physical register and it has a subreg index, use the
sub-register instead.
This fixes PR5423.
llvm-svn: 88745
2009-11-14 02:55:43 +00:00
Jim Grosbach
d7cf55cd0e
Use Unified Assembly Syntax for the ARM backend.
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llvm-svn: 86494
2009-11-09 00:11:35 +00:00
Jim Grosbach
a15c3b7124
Use aligned load/store instructions for spilling Q registers when we know the stack slot is 128 bit aligned
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llvm-svn: 86425
2009-11-08 00:27:19 +00:00
Evan Cheng
fe864425cb
Refactor code.
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llvm-svn: 86423
2009-11-08 00:15:23 +00:00
Jim Grosbach
4e9f379554
80-column cleanup of file header comments
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llvm-svn: 86408
2009-11-07 22:00:39 +00:00
Evan Cheng
a8e8a7c976
Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic.
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llvm-svn: 86330
2009-11-07 04:04:34 +00:00
Evan Cheng
b376ce0169
Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should be 22 bytes instead of 20 bytes long.
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llvm-svn: 85965
2009-11-03 23:13:34 +00:00
Evan Cheng
31c2f4701b
Trim unnecessary include.
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llvm-svn: 85878
2009-11-03 07:08:08 +00:00
Evan Cheng
23c009f125
Clean up copyRegToReg.
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llvm-svn: 85870
2009-11-03 05:51:39 +00:00
Anton Korobeynikov
d195f9e5c3
Turn neon reg-reg moves fixup code into separate pass. This should reduce the compile time.
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llvm-svn: 85850
2009-11-03 01:04:26 +00:00
Evan Cheng
1708b06c0e
Unbreak ARMBaseRegisterInfo::copyRegToReg.
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llvm-svn: 85787
2009-11-02 04:44:55 +00:00
Anton Korobeynikov
14635da94b
Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves)
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llvm-svn: 85764
2009-11-02 00:10:38 +00:00
Bob Wilson
73789b848d
Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the
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opcode and operand with a tab. Check for these instructions in the usual
places.
llvm-svn: 85411
2009-10-28 18:26:41 +00:00
Evan Cheng
5d1b849658
Don't forget subreg indices when folding load / store.
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llvm-svn: 85048
2009-10-25 07:52:27 +00:00
Evan Cheng
46ed1f8341
80 col violation.
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llvm-svn: 84986
2009-10-24 02:07:42 +00:00
Evan Cheng
0e9d9ca855
-Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed
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stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot
move above a store of spill slot #2 .
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.
llvm-svn: 84424
2009-10-18 18:16:27 +00:00
Evan Cheng
4729191bb2
Distinquish stack slots from other stack objects. They (and fixed objects) get FixedStack PseudoSourceValues.
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llvm-svn: 84326
2009-10-17 09:20:14 +00:00
Evan Cheng
8759585aba
Revert 84315 for now. Re-thinking the patch.
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llvm-svn: 84321
2009-10-17 07:53:04 +00:00
Evan Cheng
0818d87ed1
Rename getFixedStack to getStackObject. The stack objects represented are not
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necessarily fixed. Only those will negative frame indices are "fixed."
llvm-svn: 84315
2009-10-17 06:22:26 +00:00
Anton Korobeynikov
75b59fb055
Add PseudoSourceValues for constpool stuff on ELF (Darwin should use something similar)
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and register spills.
llvm-svn: 83435
2009-10-07 00:06:35 +00:00
Jakob Stoklund Olesen
dc9efe8078
Introduce the TargetInstrInfo::KILL machine instruction and get rid of the
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unused DECLARE instruction.
KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF
in the places where IMPLICIT_DEF is just used to alter liveness of physical
registers.
llvm-svn: 83006
2009-09-28 20:32:26 +00:00
Evan Cheng
83e0d481ae
Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo
...
instruction. This makes it re-materializable.
Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.
llvm-svn: 82982
2009-09-28 09:14:39 +00:00
Anton Korobeynikov
8d0fbebb9f
Add QPR_VFP2 regclass and add copy_to_regclass nodes, where needed to
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constraint the register usage.
llvm-svn: 81635
2009-09-12 22:21:08 +00:00
Anton Korobeynikov
59e2b8e894
Add NEON 'laned' operations. This fixes another bunch of gcc testsuite fails and
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makes the code faster.
llvm-svn: 81220
2009-09-08 15:22:32 +00:00
Evan Cheng
7a37b1a2ca
Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which cannot fold any immediate offset.
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llvm-svn: 80191
2009-08-27 01:23:50 +00:00
Chris Lattner
e9a75a6654
rename TAI -> MAI, being careful not to make MAILJMP instructions :)
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llvm-svn: 79777
2009-08-22 21:43:10 +00:00
Chris Lattner
7b26fce23e
Rename TargetAsmInfo (and its subclasses) to MCAsmInfo.
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llvm-svn: 79763
2009-08-22 20:48:53 +00:00
Devang Patel
0939595711
Record variable debug info at ISel time directly.
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llvm-svn: 79742
2009-08-22 17:12:53 +00:00
Jim Grosbach
841850ed26
Add Thumb2 eh_sjlj_setjmp implementation
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llvm-svn: 78701
2009-08-11 19:42:21 +00:00
Jim Grosbach
1d5350c08f
fix GetInstSizeInBytes for eh_sjlj_setjmp
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llvm-svn: 78683
2009-08-11 17:08:15 +00:00
Jim Grosbach
f24f9d9cb6
Whitespace cleanup. Remove trailing whitespace.
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llvm-svn: 78666
2009-08-11 15:33:49 +00:00
Evan Cheng
092b701a2c
Add support for folding loads / stores into 16-bit moves used by Thumb2.
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llvm-svn: 78558
2009-08-10 06:32:05 +00:00
Evan Cheng
55c014a9f3
80 col violation.
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llvm-svn: 78557
2009-08-10 05:51:48 +00:00
Anton Korobeynikov
887d05ce9b
Use VLDM / VSTM to spill/reload 128-bit Neon registers
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llvm-svn: 78468
2009-08-08 13:35:48 +00:00
Evan Cheng
2aa91cc2be
Code refactoring. No functionality change.
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llvm-svn: 78455
2009-08-08 03:20:32 +00:00
Evan Cheng
4c3b1ca5a0
Fix support to use NEON for single precision fp math.
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llvm-svn: 78397
2009-08-07 19:30:41 +00:00
Evan Cheng
b972e5633f
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
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This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
llvm-svn: 78361
2009-08-07 00:34:42 +00:00
David Goodwin
e5b5d8fbb3
When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns.
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llvm-svn: 78244
2009-08-05 21:02:22 +00:00
Chris Lattner
e98a3c3ca3
Move the getInlineAsmLength virtual method from TAI to TII, where
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the only real caller (GetFunctionSizeInBytes) uses it.
The custom ARM implementation of this is basically reimplementing
an assembler poorly for negligible gain. It should be removed
IMNSHO, but I'll leave that to ARMish folks to decide.
llvm-svn: 77877
2009-08-02 05:20:37 +00:00
Evan Cheng
e64f48ba8b
Workaround a couple of Darwin assembler bugs.
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llvm-svn: 77781
2009-08-01 06:13:52 +00:00
Evan Cheng
95d6325859
t2BR_JT is mov pc, it's 2 byte long, not 4.
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llvm-svn: 77744
2009-07-31 22:22:22 +00:00
Evan Cheng
f6d0fa3d33
- Teach TBB / TBH offset limits are 510 and 131070 respectively since the offset
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is scaled by two.
- Teach GetInstSizeInBytes about TBB and TBH.
llvm-svn: 77701
2009-07-31 18:28:05 +00:00
Evan Cheng
780748d565
- More refactoring. This gets rid of all of the getOpcode calls.
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- This change also makes it possible to switch between ARM / Thumb on a
per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.
llvm-svn: 77300
2009-07-28 05:48:47 +00:00
Evan Cheng
0e075e2429
convertToThreeAddress can't handle Thumb2 instructions (which don't have same address mode as ARM instructions).
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llvm-svn: 77230
2009-07-27 18:44:00 +00:00
Evan Cheng
8f2ed1bc5a
Clean up.
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llvm-svn: 77221
2009-07-27 18:25:24 +00:00
Evan Cheng
056c669e93
Get rid of some more getOpcode calls.
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This also fixes potential problems in ARMBaseInstrInfo routines not recognizing thumb1 instructions when 32-bit and 16-bit instructions mix.
llvm-svn: 77218
2009-07-27 18:20:05 +00:00
Evan Cheng
371ec9e810
If CPSR is modified but the def is dead, then it's ok to fold the load / store.
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llvm-svn: 77182
2009-07-27 04:18:04 +00:00
Evan Cheng
c47e109335
Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate more getOpcode calls.
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llvm-svn: 77181
2009-07-27 03:14:20 +00:00
Evan Cheng
186332f898
Use the right instructions to copy between GPR and the more strictive tGPR classes. t2MOV does not match the RC requirements.
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llvm-svn: 77175
2009-07-27 00:33:08 +00:00
Evan Cheng
0e5b149930
Merge isLoadFromStackSlot into one since it behaves the same regardless of sub-target.
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llvm-svn: 77174
2009-07-27 00:24:36 +00:00
Evan Cheng
26b51b15ed
Just use a single isMoveInstr to catch all the cases.
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llvm-svn: 77173
2009-07-27 00:05:15 +00:00
Evan Cheng
f3a1fce8ae
Change Thumb2 jumptable codegen to one that uses two level jumps:
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Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2 ]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
llvm-svn: 77024
2009-07-25 00:33:29 +00:00
Evan Cheng
666c912ce3
Make sure thumb2 jumptable entries are aligned.
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llvm-svn: 76986
2009-07-24 18:20:44 +00:00
Eli Friedman
95fc6ee51a
Remove unused member functions.
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llvm-svn: 76960
2009-07-24 07:43:59 +00:00
Evan Cheng
6cfbe61361
FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same instructions on all sub-targets.
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llvm-svn: 76925
2009-07-24 00:53:56 +00:00
David Goodwin
cdd405d804
Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.
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llvm-svn: 76919
2009-07-24 00:16:18 +00:00
Anton Korobeynikov
c5df7e2dc1
Emit cross regclass register moves for thumb2.
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Minor code duplication cleanup.
llvm-svn: 76124
2009-07-16 23:26:06 +00:00
Torok Edwin
fbcc663cbf
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
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This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
llvm-svn: 75640
2009-07-14 16:55:14 +00:00
Torok Edwin
56d0659726
assert(0) -> LLVM_UNREACHABLE.
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Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.
llvm-svn: 75379
2009-07-11 20:10:48 +00:00
Evan Cheng
bf041366c4
80 col violation.
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llvm-svn: 75358
2009-07-11 06:37:27 +00:00
Evan Cheng
3b88dd6900
Move isPredicated from .cpp to .h
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llvm-svn: 75217
2009-07-10 01:38:27 +00:00
Evan Cheng
e3a53c448b
Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead.
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llvm-svn: 75048
2009-07-08 21:03:57 +00:00
David Goodwin
af7451b674
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
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llvm-svn: 75010
2009-07-08 16:09:28 +00:00