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291 Commits

Author SHA1 Message Date
Jim Grosbach 7ef7ddd2df Clean up a few 80 column violations. 
llvm-svn: 132946
 2011-06-13 22:54:22 +00:00
Andrew Trick 410172bf5e Fix for setjmp/longjmp exception handling on ARM. setjmp clobbers CPSR. 
rdar://problem/9556069

llvm-svn: 132699
 2011-06-07 00:08:49 +00:00
Eric Christopher 9b67db8ea7 Make the branch encoding for tBcc more obvious that it's a 4-byte opcode 
followed by a conditional and imm8.

llvm-svn: 132179
 2011-05-27 03:50:53 +00:00
Cameron Zwarich 26ddb12118 Mark tBX as an indirect branch rather than a return. 
llvm-svn: 132107
 2011-05-26 03:41:12 +00:00
Cameron Zwarich a946f476d3 Convert tBX_CALL / tBXr9_CALL to actual pseudoinstructions. 
llvm-svn: 132086
 2011-05-25 21:53:50 +00:00
Cameron Zwarich 6b66ee1865 Move some code to a more logical place. 
llvm-svn: 132043
 2011-05-25 04:45:29 +00:00
Cameron Zwarich 310b3472ec Change the order of tBX's operands so that the predicate operands come after the 
target register, matching BX. I filed this bug because I was confused at first:

PR10007 - ARM branch instructions have inconsistent predicate operand placement
<http://llvm.org/bugs/show_bug.cgi?id=10007>

llvm-svn: 132041
 2011-05-25 04:45:23 +00:00
Cameron Zwarich 012247e60c Rename tBX_Rm to tBX. 
llvm-svn: 132040
 2011-05-25 04:45:20 +00:00
Cameron Zwarich deaf994ff0 Rename the existing tBX/tBXr9 instructions to tBX_CALL/tBXr9_CALL to better 
reflect their actual meaning and match the ARM instructions.

llvm-svn: 132039
 2011-05-25 04:45:14 +00:00
Owen Anderson b745623b71 Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan. 
llvm-svn: 131189
 2011-05-11 17:00:48 +00:00
Jakob Stoklund Olesen f8be385c9b Mark ultra-super-registers QQQQ as call-clobbered instead of the D sub-registers. 
LiveVariables doesn't understand that clobbering D0 and D1 completely overwrites
Q0, so if Q0 is live-in to a function, its live range will extend beyond a
function call that only clobbers D0 and D1. This shows up in the
ARM/2009-11-01-NeonMoves test case.

LiveVariables should probably implement the much stricter rules for physreg
liveness that RAFast imposes - a physreg is killed by the first use of any
alias.

llvm-svn: 130801
 2011-05-03 22:31:24 +00:00
Bruno Cardoso Lopes 86c6e7057d Fold ARM coprocessor intrinsics patterns into the instructions defs whenever 
it's possible.

llvm-svn: 130764
 2011-05-03 17:29:29 +00:00
Bruno Cardoso Lopes 168c9005b5 Add a few ARM coprocessor intrinsics. Testcases included 
llvm-svn: 130763
 2011-05-03 17:29:22 +00:00
Eric Christopher a98cd22d96 Let the immediate leaf pattern take transforms and switch the signed 
immediate patterns in arm to using the pattern.

Handles rdar://9299434

llvm-svn: 130386
 2011-04-28 05:49:04 +00:00
Johnny Chen 57c892860e Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should 
print out ldr, not ldr.n.

rdar://problem/9267772

llvm-svn: 130008
 2011-04-22 19:12:43 +00:00
Chris Lattner 0ab5e2cded Fix a ton of comment typos found by codespell. Patch by 
Luis Felipe Strano Moraes!

llvm-svn: 129558
 2011-04-15 05:18:47 +00:00
Evan Cheng 44887f9c7e Follow up on r127913. Fix Thumb revsh isel. rdar://9286766 
llvm-svn: 129548
 2011-04-14 23:27:44 +00:00
Johnny Chen dc8bf9ec08 Thumb disassembler was erroneously rejecting "blx sp" instruction. 
rdar://problem/9267838

llvm-svn: 129320
 2011-04-11 23:33:30 +00:00
Bruno Cardoso Lopes f922b20922 Change MRC and MRC2 instructions to model the output register properly 
llvm-svn: 128085
 2011-03-22 15:06:24 +00:00
Bruno Cardoso Lopes 90d1dfe4c6 Fix encoding and add parsing support for the arm/thumb CPS instruction: 
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
  from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
  wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.

llvm-svn: 125489
 2011-02-14 13:09:44 +00:00
Bruno Cardoso Lopes d8f9b37f31 Add cdp/cdp2 instructions for thumb/thumb2 
llvm-svn: 123929
 2011-01-20 18:32:09 +00:00
Bruno Cardoso Lopes cf99dc7eb9 Add mcr* and mr*c support to thumb targets 
llvm-svn: 123917
 2011-01-20 16:35:57 +00:00
Chris Lattner 2a0a3b43d7 Flag -> Glue, the ongoing saga 
llvm-svn: 122513
 2010-12-23 18:28:41 +00:00
Bill Wendling cdcc4fc048 Fix a copy-pasto. When the tBR_JTr instruction was converted to using the 
tPseudoInst class, its size was changed from "special" to "2 bytes". This is
incorrect because the jump table will no longer be taken into account when
calculating branch offsets.
<rdar://problem/8782216>

llvm-svn: 122303
 2010-12-21 01:57:15 +00:00
Jim Grosbach b5743b9d76 Pseudo-ize the Thumb1 tBfar pattern. rdar://8777974 
llvm-svn: 121990
 2010-12-16 19:11:16 +00:00
Bill Wendling f5b17c32d2 Add encodings for Thumb1 Spill and Restore pseudos. 
llvm-svn: 121929
 2010-12-16 00:38:41 +00:00
Jim Grosbach bfef309d11 Thumb1 had two patterns for the same load-from-constant-pool instruction. 
Canonicalize on tLDRpci and remove tLDRcp.

llvm-svn: 121920
 2010-12-15 23:52:36 +00:00
Bill Wendling 6217ecd634 Whitespace cleanups. 
llvm-svn: 121914
 2010-12-15 23:31:24 +00:00
Bill Wendling 1171e9e81d Add some missing patterns now that tLDRB and tLDRH are split into reg and 
immediate versions.

llvm-svn: 121819
 2010-12-15 00:58:57 +00:00
Bill Wendling 5ab38b59e6 Comments and cleaning. 
llvm-svn: 121809
 2010-12-14 23:42:48 +00:00
Jim Grosbach 509dc2a700 Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755 
llvm-svn: 121798
 2010-12-14 22:28:03 +00:00
Bill Wendling ce4f87b3ba Multiclassify the LDR/STR encoding patterns. The only functionality difference 
is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.

llvm-svn: 121794
 2010-12-14 22:10:49 +00:00
Bill Wendling 6dd0c07622 Use the integer scheduling intrinsic for integer loads and stores. 
llvm-svn: 121765
 2010-12-14 12:33:05 +00:00
Bill Wendling 092a7bdf9f The tLDR et al instructions were emitting either a reg/reg or reg/imm 
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.

The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.

There are some obvious cleanups here, which will happen shortly.

llvm-svn: 121747
 2010-12-14 03:36:38 +00:00
Owen Anderson b0fa127f60 Fix encoding of Thumb1 LDRB and STRB. 
llvm-svn: 121581
 2010-12-10 22:11:13 +00:00
Jim Grosbach e119da1146 Thumb unconditional branch binary encoding. rdar://8754994 
llvm-svn: 121496
 2010-12-10 18:21:33 +00:00
Jim Grosbach 78485ad65e Thumb conditional branch binary encodings. rdar://8745367 
llvm-svn: 121493
 2010-12-10 17:13:40 +00:00
Bill Wendling 0c4838bab7 Thumb ldr reg+imm offsets were encoded incorrectly. The scaling factor of the 
t_addrmode_s# address modes is used for ASM printing, not for encoding.
<rdar://problem/8745375>

llvm-svn: 121417
 2010-12-09 21:49:07 +00:00
Jim Grosbach 62b68112da Rename the encoder method for t_cbtarget to match. 
llvm-svn: 121399
 2010-12-09 19:04:53 +00:00
Jim Grosbach 529c7e8d1f Thumb needs a few different encoding schemes for branch targets. Rename 
t_brtarget to be more specific.

llvm-svn: 121398
 2010-12-09 19:01:46 +00:00
Bill Wendling 3392bfc8f3 The BLX instruction is encoded differently than the BL, because why not? In 
particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0'
always. Going through the BL fixup encoding was trashing the "bit 0 is '0'"
invariant.

Attempt to get the encoding at slightly more correct with this.

llvm-svn: 121336
 2010-12-09 00:39:08 +00:00
Bill Wendling a7d6aa902a Support the "target" encodings for the CB[N]Z instructions. 
llvm-svn: 121308
 2010-12-08 23:01:43 +00:00
Bill Wendling 8a6449c46e Add support for loading from a constant pool. 
llvm-svn: 121226
 2010-12-08 01:57:09 +00:00
Jim Grosbach 49bcd6ff85 Binary encoding for ARM tLDRspi and tSTRspi. 
llvm-svn: 121186
 2010-12-07 21:50:47 +00:00
Jim Grosbach 327cf8ee5f Refactor the ARM CMPz* patterns to just use the normal CMP instructions when 
possible. They were duplicates for everything exception the source pattern
before.

llvm-svn: 121179
 2010-12-07 20:41:06 +00:00
Jim Grosbach 6e517d658e Encode the literal field for tCMPzi instruction. 
llvm-svn: 121153
 2010-12-07 17:48:24 +00:00
Jim Grosbach 9e1994698d Add fixup for Thumb1 BL/BLX instructions. 
llvm-svn: 121072
 2010-12-06 23:57:07 +00:00
Jim Grosbach ce18d7ebb5 Encode condition code for Thumb1 conditional branch instruction. 
llvm-svn: 120865
 2010-12-04 00:20:40 +00:00
Bill Wendling 127d7485f1 Use correct variable names to match the patterns. 
llvm-svn: 120857
 2010-12-03 23:44:24 +00:00
Jim Grosbach a09cbbeef5 Match pattern operand names to expected encoding field names. This corrects the 
operand encoding ordering of the instruction.

llvm-svn: 120852
 2010-12-03 23:21:25 +00:00