Commit Graph

95101 Commits

Author SHA1 Message Date
Elena Demikhovsky 33d447a2d6 AVX-512: Added SHIFT instructions.
llvm-svn: 188899
2013-08-21 09:36:02 +00:00
Richard Sandiford 7d86e47d04 [SystemZ] Define remainig *MUL_LOHI patterns
The initial port used MLG(R) for i64 UMUL_LOHI but left the other three
combinations as not-legal-or-custom.  Although 32x32->{32,32}
multiplications exist, they're not as quick as doing a normal 64-bit
multiplication, so it didn't seem like i32 SMUL_LOHI and UMUL_LOHI
would be useful.  There's also no direct instruction for i64 SMUL_LOHI,
so it needs to be implemented in terms of UMUL_LOHI.

However, not defining these patterns means that we don't convert
division by a constant into multiplication, so this patch fills
in the other cases.  The new i64 SMUL_LOHI sequence is simpler
than the one that we used previously for 64x64->128 multiplication,
so int-mul-08.ll now tests the full sequence.

llvm-svn: 188898
2013-08-21 09:34:56 +00:00
NAKAMURA Takumi ca2cbc9836 MCFunction.h: Prune \returns to fix a warning in r188881. [-Wdocumentation]
llvm-svn: 188897
2013-08-21 09:34:22 +00:00
Daniel Sanders 41194e3f9e [mips][msa] Matheus Almeida pointed out a silly mistake in r188893. Fixed it.
I accidentally changed the encoding of the MSA registers to zero instead of 0
to 31. This change restores the encoding the registers had prior to r188893.

This didn't show up in the existing tests because direct-object emission isn't
implemented yet for MSA.

llvm-svn: 188896
2013-08-21 09:09:52 +00:00
Richard Sandiford af5f66ac9e [SystemZ] Use FI[EDX]BRA for codegen
llvm-svn: 188895
2013-08-21 09:04:20 +00:00
Richard Sandiford 8e92c389e4 [SystemZ] Add FI[EDX]BRA
These are extensions of the existing FI[EDX]BR instructions, but use a spare
bit to suppress inexact conditions.

llvm-svn: 188894
2013-08-21 08:58:08 +00:00
Daniel Sanders ec12322a28 [mips][msa] Define registers using foreach
No functional change

llvm-svn: 188893
2013-08-21 08:48:25 +00:00
Ahmed Bougacha 1792647942 MC CFG: Add YAML MCModule representation to enable MC CFG testing.
Like yaml ObjectFiles, this will be very useful for testing the MC CFG
implementation (mostly MCObjectDisassembler), by matching the output
with YAML, and for potential users of the MC CFG, by using it as an input.

There isn't much to the actual format, it is just a serialization of the
MCModule class. Of note:
  - Basic block references (pred/succ, ..) are represented by the BB's
    start address.
  - Just as in the MC CFG, instructions are MCInsts with a size.
  - Operands have a prefix representing the type (only register and
    immediate supported here).
  - Instruction opcodes are represented by their names; enum values aren't
    stable, enum names mostly are: usually, a change to a name would need
    lots of changes in the backend anyway.
    Same with registers.

All in all, an example is better than 1000 words, here goes:

A simple binary:

  Disassembly of section __TEXT,__text:
  _main:
  100000f9c:      48 8b 46 08             movq    8(%rsi), %rax
  100000fa0:      0f be 00                movsbl  (%rax), %eax
  100000fa3:      3b 04 25 48 00 00 00    cmpl    72, %eax
  100000faa:      0f 8c 07 00 00 00       jl      7 <.Lend>
  100000fb0:      2b 04 25 48 00 00 00    subl    72, %eax
  .Lend:
  100000fb7:      c3                      ret

And the (pretty verbose) generated YAML:

  ---
  Atoms:
    - StartAddress:    0x0000000100000F9C
      Size:            20
      Type:            Text
      Content:
        - Inst:            MOV64rm
          Size:            4
          Ops:             [ RRAX, RRSI, I1, R, I8, R ]
        - Inst:            MOVSX32rm8
          Size:            3
          Ops:             [ REAX, RRAX, I1, R, I0, R ]
        - Inst:            CMP32rm
          Size:            7
          Ops:             [ REAX, R, I1, R, I72, R ]
        - Inst:            JL_4
          Size:            6
          Ops:             [ I7 ]
    - StartAddress:    0x0000000100000FB0
      Size:            7
      Type:            Text
      Content:
        - Inst:            SUB32rm
          Size:            7
          Ops:             [ REAX, REAX, R, I1, R, I72, R ]
    - StartAddress:    0x0000000100000FB7
      Size:            1
      Type:            Text
      Content:
        - Inst:            RET
          Size:            1
          Ops:             [  ]
  Functions:
    - Name:            __text
      BasicBlocks:
        - Address:         0x0000000100000F9C
          Preds:           [  ]
          Succs:           [ 0x0000000100000FB7, 0x0000000100000FB0 ]
     <snip>
  ...

llvm-svn: 188890
2013-08-21 07:29:02 +00:00
Ahmed Bougacha 69a7562335 MC CFG: Support disassembly at arbitrary addresses in MCObjectDisassembler.
llvm-svn: 188889
2013-08-21 07:28:55 +00:00
Ahmed Bougacha 518cc6f811 MC CFG: Use data structures more appropriate than std::set.
llvm-svn: 188888
2013-08-21 07:28:51 +00:00
Ahmed Bougacha 58ed11341b MC CFG: Add an MCObjectSymbolizer in the MCObjectDisassembler.
Used to detect calls to function symbol stubs (future commit).

llvm-svn: 188887
2013-08-21 07:28:48 +00:00
Ahmed Bougacha b09d140f6b MC CFG: Add MCObjectDisassembler Mach-O implementation.
Supports:
- entrypoint, using LC_MAIN.
- static ctors/dtors, using __mod_{init,exit}_func
- translation between effective and object load address, using
  dyld's VM address slide.

llvm-svn: 188886
2013-08-21 07:28:44 +00:00
Ahmed Bougacha 0a89d2bf76 Add Mach-O entry_point_command declaration.
llvm-svn: 188885
2013-08-21 07:28:40 +00:00
Ahmed Bougacha 2eb593682a MC CFG: Add "dynamic disassembly" support to MCObjectDisassembler.
It can now disassemble code in situations where the effective load
address is different than the load address declared in the object file.
This happens for PIC, hence "dynamic".

llvm-svn: 188884
2013-08-21 07:28:37 +00:00
Ahmed Bougacha 57bc9677cd MC CFG: When disassembly is impossible, fallback to data bytes.
This is the behavior of sequential disassemblers (llvm-objdump, ...),
when there is no instruction size hint (fixed-length, ...)

While there, also do some minor cleanup.

llvm-svn: 188883
2013-08-21 07:28:32 +00:00
Ahmed Bougacha a376353346 MC CFG: Add MCObjectDisassembler support for entrypoint + static ctors.
For now, this isn't implemented for any format.

llvm-svn: 188882
2013-08-21 07:28:29 +00:00
Ahmed Bougacha ff12d02d51 MC CFG: Split MCBasicBlocks to mirror atom splitting.
When an MCTextAtom is split, all MCBasicBlocks backed by it are
automatically split, with a fallthrough between both blocks, and
the successors moved to the second block.

llvm-svn: 188881
2013-08-21 07:28:24 +00:00
Ahmed Bougacha d3fc5b9648 MC CFG: Add a few needed methods, mainly MCModule::findFirstAtomAfter.
While there, do some minor cleanup.

llvm-svn: 188880
2013-08-21 07:28:17 +00:00
Ahmed Bougacha ffeecb5c80 MC: ObjectSymbolizer can now recognize external function stubs.
Only implemented in the Mach-O ObjectSymbolizer.
The testcase sadly introduces a new binary.

llvm-svn: 188879
2013-08-21 07:28:13 +00:00
Ahmed Bougacha 382a6d7562 MC: Refactor ObjectSymbolizer to make relocation/section info generation lazy.
llvm-svn: 188878
2013-08-21 07:28:07 +00:00
Ahmed Bougacha 630f9546c0 MC CFG: Add entrypoint address to MCModule.
llvm-svn: 188877
2013-08-21 07:28:02 +00:00
Ahmed Bougacha 3012ac5387 MC CFG: Add more MCFunction container methods (find, empty).
llvm-svn: 188876
2013-08-21 07:27:59 +00:00
Ahmed Bougacha 7bfc7da6e8 MC CFG: Keep pointer to parent MCModule in created MCFunctions.
Also, drive-by cleaning around createFunction.

llvm-svn: 188875
2013-08-21 07:27:55 +00:00
Ahmed Bougacha d6351e76d5 MC CFG: Don't insert preds/succs again.
llvm-svn: 188874
2013-08-21 07:27:50 +00:00
Ahmed Bougacha c43aa4e88c MC CFG: Remap enough for the inserted instruction.
llvm-svn: 188873
2013-08-21 07:27:47 +00:00
Ahmed Bougacha 03efde5887 MC CFG: uint64_t -> size_t for vector size.
llvm-svn: 188872
2013-08-21 07:27:44 +00:00
Ahmed Bougacha 729ad51905 MC CFG: Add a getter for MCDataAtom's data array.
While there, switch to new-style documentation.

llvm-svn: 188871
2013-08-21 07:27:40 +00:00
David Majnemer ed89b5c6e7 DebugInfo: Do not use the DWARF Version for the .debug_pubnames or .debug_pubtypes version field
Summary:
LLVM would generate DWARF with version 3 in the .debug_pubname and
.debug_pubtypes version fields.  This would lead SGI dwarfdump to fail
parsing the DWARF with (in the instance of .debug_pubnames) would exit
with:
dwarfdump ERROR:  dwarf_get_globals: DW_DLE_PUBNAMES_VERSION_ERROR (123)

This fixes PR16950.

Reviewers: echristo, dblaikie

Reviewed By: echristo

CC: cfe-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1454

llvm-svn: 188869
2013-08-21 06:13:34 +00:00
Craig Topper 77df9cdd0b Synchronize VEX JIT encoding code with the MCJIT version. Fix a bug in the MCJIT code where CurOp was being incremented even if the operand it was pointing at wasn't used. Maybe only matters if there are any EVEX_K instructions that aren't VEX_4V.
llvm-svn: 188868
2013-08-21 05:57:45 +00:00
Nadav Rotem 7efc04cb40 In LLVM FMA3 operands are dst, src1, src2, src3, however dst is not encoded as it is always src1. This was causing the encoding of the operands to be off by one.
Patch by Chris Bieneman.

llvm-svn: 188866
2013-08-21 05:03:10 +00:00
Nadav Rotem 092559e6f0 Add the FMA3 feature in order to test FMA encoding using the old jit.
Patch by Chris Bieneman!

llvm-svn: 188865
2013-08-21 05:02:12 +00:00
Craig Topper 5c94bb8551 Rename mattr names for AVX-512 to from avx-512 -> avx512f, avx-512-pfi -> av512pf, avx-512-cdi -> avx512cd, avx-512-eri->avx512er. This matches better with official docs and what gcc patches appearto be using. I didn't touch the has* functions or the feature flag names to avoid change the td and lowering file while commits are still happening.
llvm-svn: 188859
2013-08-21 03:57:57 +00:00
NAKAMURA Takumi de8880a23d X86TargetMachine.cpp: Clarify to emit GOT in i686-{cygming|win32}-elf for mcjit.
I suppose all "lli -use-mcjit i686-*" should require GOT, (and to fail.)

llvm-svn: 188856
2013-08-21 02:37:25 +00:00
NAKAMURA Takumi b46d3c8995 lli/RecordingMemoryManager.cpp: Make it complain if _GLOBAL_OFFSET_TABLE_ were not provided.
FIXME: Would it be responsible to provide GOT?
llvm-svn: 188855
2013-08-21 02:37:14 +00:00
Jakub Staszak 84a0ae74b0 Move #includes from .h to .cpp file.
llvm-svn: 188852
2013-08-21 01:20:11 +00:00
Akira Hatanaka 39f915b58a [micromips] Print instruction alias "not" if the last operand of a nor is zero.
llvm-svn: 188851
2013-08-21 01:18:46 +00:00
Bill Wendling 707f601fa5 Move registering the execution of a basic block to the beginning rather than the end.
There are situations which can affect the correctness (or at least expectation)
of the gcov output. For instance, if a call to __gcov_flush() occurs within a
block before the execution count is registered and then the program aborts in
some way, then that block will not be marked as executed. This is not normally
what the user expects.

If we move the code that's registering when a block is executed to the
beginning, we can catch these types of situations.

PR16893

llvm-svn: 188849
2013-08-20 23:52:00 +00:00
Akira Hatanaka 9a1fb6b9fc [mips] Add support for mfhc1 and mthc1.
llvm-svn: 188848
2013-08-20 23:47:25 +00:00
Akira Hatanaka bfb6624797 [mips] Add support for calling convention CC_MipsO32_FP64, which is used when the
size of floating point registers is 64-bit.

Test case will be added when support for mfhc1 and mthc1 is added.

llvm-svn: 188847
2013-08-20 23:38:40 +00:00
Akira Hatanaka 8dd951bc9f [mips] Remove predicates that were incorrectly or unnecessarily added.
llvm-svn: 188845
2013-08-20 23:21:55 +00:00
Jakub Staszak d184e2decc Add some constantness.
llvm-svn: 188844
2013-08-20 23:04:15 +00:00
Bill Wendling 0911248b8d Use -disable-output and to suppress output and don't use a temporary file unless we need one.
llvm-svn: 188843
2013-08-20 23:00:25 +00:00
Akira Hatanaka 14e31a2fe7 [mips] Define register class FGRH32 for the high half of the 64-bit floating
point registers. We will need this register class later when we add
definitions for instructions mfhc1 and mthc1. Also, remove sub-register indices
sub_fpeven and sub_fpodd and use sub_lo and sub_hi instead.

llvm-svn: 188842
2013-08-20 22:58:56 +00:00
Jakub Staszak 906e48f2a0 Fix include guards.
llvm-svn: 188841
2013-08-20 22:52:02 +00:00
Arnold Schwaighofer e1f3ab69d1 SLPVectorizer: Fix invalid iterator errors
Update iterator when the SLP vectorizer changes the instructions in the basic
block by restarting the traversal of the basic block.

Patch by Yi Jiang!

Fixes PR 16899.

llvm-svn: 188832
2013-08-20 21:21:45 +00:00
Matt Arsenault 7a960a8455 Teach ConstantFolding about pointer address spaces
llvm-svn: 188831
2013-08-20 21:20:04 +00:00
Akira Hatanaka 6781fc1648 [mips] Resolve register classes dynamically using ptr_rc to reduce the number of
load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.

llvm-svn: 188830
2013-08-20 21:08:22 +00:00
Reed Kotler d8f3362557 Add an option which permits the user to specify using a bitmask, that various
functions be compiled as mips32, without having to add attributes. This
is useful in certain situations where you don't want to have to edit the
function attributes in the source. For now it's only an option used for
the compiler developers when debugging the mips16 port.

llvm-svn: 188826
2013-08-20 20:53:09 +00:00
Akira Hatanaka a43b56d9af [mips] Guard micromips instructions with predicate InMicroMips. Also, fix
assembler predicate HasStdEnd so that it is false when the target is micromips.

llvm-svn: 188824
2013-08-20 20:46:51 +00:00
Jim Grosbach 71a78f962b ARM: Fix fast-isel copy/paste-o.
Update testcase to be more careful about checking register
values. While regexes are general goodness for these sorts of
testcases, in this example, the registers are constrained by
the calling convention, so we can and should check their
explicit values.

rdar://14779513

llvm-svn: 188819
2013-08-20 19:12:42 +00:00
Andrew Kaylor 00b8fe583d Still more MCJIT PIC test XFAILs
llvm-svn: 188815
2013-08-20 18:13:48 +00:00
Andrew Kaylor c20ace87fa Clarifying two MCJIT PIC tests as XFAIL on i686-pc-linux
llvm-svn: 188814
2013-08-20 17:01:35 +00:00
Andrew Kaylor fae66f2aa8 Removing duplicate XFAIL markers
llvm-svn: 188812
2013-08-20 16:42:22 +00:00
Andrew Kaylor cf90777cd0 Marking two more MCJIT PIC tests as XFAIL on i686
llvm-svn: 188808
2013-08-20 15:47:04 +00:00
Andrew Kaylor e35613b962 Marking MCJIT PIC tests as XFAIL on arm
llvm-svn: 188807
2013-08-20 15:36:04 +00:00
Vladimir Medic 9bad0d33b6 Fix style issues in AsmParser.cpp
llvm-svn: 188798
2013-08-20 13:33:18 +00:00
Elena Demikhovsky 540d582594 AVX-512: Added more patterns for VMOVSS, VMOVSD, VMOVD, VMOVQ
llvm-svn: 188786
2013-08-20 11:00:29 +00:00
Daniel Sanders 4260527f5f [mips][msa] Removed fcge, fcgt, fsge, fsgt
These instructions were present in a draft spec but were removed before
publication.

llvm-svn: 188782
2013-08-20 09:41:47 +00:00
Richard Sandiford 2bf7b8cc4e [SystemZ] Update README
We now use MVST, CLST and SRST for the obvious cases.

llvm-svn: 188781
2013-08-20 09:40:35 +00:00
Richard Sandiford 6f6d55161b [SystemZ] Use SRST to optimize memchr
SystemZTargetLowering::emitStringWrapper() previously loaded the character
into R0 before the loop and made R0 live on entry.  I'd forgotten that
allocatable registers weren't allowed to be live across blocks at this stage,
and it confused LiveVariables enough to cause a miscompilation of f3 in
memchr-02.ll.

This patch instead loads R0 in the loop and leaves LICM to hoist it
after RA.  This is actually what I'd tried originally, but I went for
the manual optimisation after noticing that R0 often wasn't being hoisted.
This bug forced me to go back and look at why, now fixed as r188774.

We should also try to optimize null checks so that they test the CC result
of the SRST directly.  The select between null and the SRST GPR result could
then usually be deleted as dead.

llvm-svn: 188779
2013-08-20 09:38:48 +00:00
Benjamin Kramer 5a71250113 memcmp is not a valid way to compare structs with padding in them.
llvm-svn: 188778
2013-08-20 09:27:31 +00:00
Daniel Sanders f2a0f1d133 [mips][msa] Added insve
llvm-svn: 188777
2013-08-20 09:22:54 +00:00
Richard Sandiford bdd81d76f8 Fix test typo and add usual "br %r14" test
llvm-svn: 188775
2013-08-20 09:14:46 +00:00
Richard Sandiford 96aa93d5f1 Fix overly pessimistic shortcut in post-RA MachineLICM
Post-RA LICM keeps three sets of registers: PhysRegDefs, PhysRegClobbers
and TermRegs.  When it sees a definition of R it adds all aliases of R
to the corresponding set, so that when it needs to test for membership
it only needs to test a single register, rather than worrying about
aliases there too.  E.g. the final candidate loop just has:

    unsigned Def = Candidates[i].Def;
    if (!PhysRegClobbers.test(Def) && ...) {

to test whether register Def is multiply defined.

However, there was also a shortcut in ProcessMI to make sure we didn't
add candidates if we already knew that they would fail the final test.
This shortcut was more pessimistic than the final one because it
checked whether _any alias_ of the defined register was multiply defined.
This is too conservative for targets that define register pairs.
E.g. on z, R0 and R1 are sometimes used as a pair, so there is a
128-bit register that aliases both R0 and R1.  If a loop used
R0 and R1 independently, and the definition of R0 came first,
we would be able to hoist the R0 assignment (because that used
the final test quoted above) but not the R1 assignment (because
that meant we had two definitions of the paired R0/R1 register
and would fail the shortcut in ProcessMI).

This patch just uses the same check for the ProcessMI shortcut as
we use in the final candidate loop.

llvm-svn: 188774
2013-08-20 09:11:13 +00:00
Tim Northover f79c3a5aef ARM: implement some simple f64 materializations.
Previously we used a const-pool load for virtually all 64-bit floating values.
Actually, we can get quite a few common values (including 0.0, 1.0) via "vmov"
instructions of one stripe or another.

llvm-svn: 188773
2013-08-20 08:57:11 +00:00
Michael Gottesman dc985ef0af [stackprotector] Small cleanup.
llvm-svn: 188772
2013-08-20 08:56:28 +00:00
Michael Gottesman 76c44be14a [stackprotector] Small Bit of computation hoisting.
llvm-svn: 188771
2013-08-20 08:56:26 +00:00
Michael Gottesman 1977d15e02 [stackprotector] Added significantly longer comment to FindPotentialTailCall to make clear its relationship to llvm::isInTailCallPosition.
llvm-svn: 188770
2013-08-20 08:56:23 +00:00
Michael Gottesman 62c5d714a1 Removed trailing whitespace.
llvm-svn: 188769
2013-08-20 08:46:16 +00:00
Michael Gottesman 56e246b1a1 [stackprotector] Removed stale TODO.
llvm-svn: 188768
2013-08-20 08:46:13 +00:00
Daniel Sanders 869bdad93a [mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v
llvm-svn: 188767
2013-08-20 08:38:21 +00:00
Michael Gottesman 5e57068b7a [stackprotector] Added support for emitting the llvm intrinsic stack protector check.
rdar://13935163

llvm-svn: 188766
2013-08-20 08:36:53 +00:00
Michael Gottesman ce0e4c263b [stackprotector] Refactor out the end of isInTailCallPosition into the function returnTypeIsEligibleForTailCall.
This allows me to use returnTypeIsEligibleForTailCall in the stack protector pass.

rdar://13935163

llvm-svn: 188765
2013-08-20 08:36:50 +00:00
Michael Gottesman f7e1203d95 Remove unused variables that crept in.
llvm-svn: 188761
2013-08-20 07:17:27 +00:00
Michael Gottesman b27f0f1f6b Teach selectiondag how to handle the stackprotectorcheck intrinsic.
Previously, generation of stack protectors was done exclusively in the
pre-SelectionDAG Codegen LLVM IR Pass "Stack Protector". This necessitated
splitting basic blocks at the IR level to create the success/failure basic
blocks in the tail of the basic block in question. As a result of this,
calls that would have qualified for the sibling call optimization were no
longer eligible for optimization since said calls were no longer right in
the "tail position" (i.e. the immediate predecessor of a ReturnInst
instruction).

Then it was noticed that since the sibling call optimization causes the
callee to reuse the caller's stack, if we could delay the generation of
the stack protector check until later in CodeGen after the sibling call
decision was made, we get both the tail call optimization and the stack
protector check!

A few goals in solving this problem were:

  1. Preserve the architecture independence of stack protector generation.

  2. Preserve the normal IR level stack protector check for platforms like
     OpenBSD for which we support platform specific stack protector
     generation.

The main problem that guided the present solution is that one can not
solve this problem in an architecture independent manner at the IR level
only. This is because:

  1. The decision on whether or not to perform a sibling call on certain
     platforms (for instance i386) requires lower level information
     related to available registers that can not be known at the IR level.

  2. Even if the previous point were not true, the decision on whether to
     perform a tail call is done in LowerCallTo in SelectionDAG which
     occurs after the Stack Protector Pass. As a result, one would need to
     put the relevant callinst into the stack protector check success
     basic block (where the return inst is placed) and then move it back
     later at SelectionDAG/MI time before the stack protector check if the
     tail call optimization failed. The MI level option was nixed
     immediately since it would require platform specific pattern
     matching. The SelectionDAG level option was nixed because
     SelectionDAG only processes one IR level basic block at a time
     implying one could not create a DAG Combine to move the callinst.

To get around this problem a few things were realized:

  1. While one can not handle multiple IR level basic blocks at the
     SelectionDAG Level, one can generate multiple machine basic blocks
     for one IR level basic block. This is how we handle bit tests and
     switches.

  2. At the MI level, tail calls are represented via a special return
     MIInst called "tcreturn". Thus if we know the basic block in which we
     wish to insert the stack protector check, we get the correct behavior
     by always inserting the stack protector check right before the return
     statement. This is a "magical transformation" since no matter where
     the stack protector check intrinsic is, we always insert the stack
     protector check code at the end of the BB.

Given the aforementioned constraints, the following solution was devised:

  1. On platforms that do not support SelectionDAG stack protector check
     generation, allow for the normal IR level stack protector check
     generation to continue.

  2. On platforms that do support SelectionDAG stack protector check
     generation:

    a. Use the IR level stack protector pass to decide if a stack
       protector is required/which BB we insert the stack protector check
       in by reusing the logic already therein. If we wish to generate a
       stack protector check in a basic block, we place a special IR
       intrinsic called llvm.stackprotectorcheck right before the BB's
       returninst or if there is a callinst that could potentially be
       sibling call optimized, before the call inst.

    b. Then when a BB with said intrinsic is processed, we codegen the BB
       normally via SelectBasicBlock. In said process, when we visit the
       stack protector check, we do not actually emit anything into the
       BB. Instead, we just initialize the stack protector descriptor
       class (which involves stashing information/creating the success
       mbbb and the failure mbb if we have not created one for this
       function yet) and export the guard variable that we are going to
       compare.

    c. After we finish selecting the basic block, in FinishBasicBlock if
       the StackProtectorDescriptor attached to the SelectionDAGBuilder is
       initialized, we first find a splice point in the parent basic block
       before the terminator and then splice the terminator of said basic
       block into the success basic block. Then we code-gen a new tail for
       the parent basic block consisting of the two loads, the comparison,
       and finally two branches to the success/failure basic blocks. We
       conclude by code-gening the failure basic block if we have not
       code-gened it already (all stack protector checks we generate in
       the same function, use the same failure basic block).

llvm-svn: 188755
2013-08-20 07:00:16 +00:00
Craig Topper 7a8cf01090 Fix formatting. No functional change.
llvm-svn: 188746
2013-08-20 05:23:59 +00:00
Craig Topper e13a066c94 Add AVX-512 and related features to the CPUID detection code.
llvm-svn: 188745
2013-08-20 05:22:42 +00:00
Craig Topper fd2b389263 Move AVX and non-AVX replication inside a couple multiclasses to avoid repeating each instruction for both individually.
llvm-svn: 188743
2013-08-20 04:24:14 +00:00
Craig Topper 998a39aeed Add an error check for a typo I accidentally made in a td file that caused an assert to fire.
llvm-svn: 188742
2013-08-20 04:22:09 +00:00
Bill Schmidt f381afc906 [PowerPC] More refactoring prior to real PPC emitPrologue/Epilogue changes.
(Patch committed on behalf of Mark Minich, whose log entry follows.)

This is a continuation of the refactorings performed in svn rev 188573
(see that rev's comments for more detail).

This is my stage 2 refactoring: I combined the emitPrologue() &
emitEpilogue() PPC32 & PPC64 code into a single flow, simplifying a
lot of the code since in essence the PPC32 & PPC64 code generation
logic is the same, only the instruction forms are different (in most
cases). This simplification is necessary because my functional changes
(yet to come) add significant complexity, and without the
simplification of my stage 2 refactoring, the overall complexity of
both emitPrologue() & emitEpilogue() would have become almost
intractable for most mortal programmers (like me).

This submission was intended to be a pure refactoring (no functional
changes whatsoever). However, in the process of combining the PPC32 &
PPC64 flows, I spotted a difference that I believe is a bug (see svn
rev 186478 line 863, or svn rev 188573 line 888): This line appears to
be restoring the BP with the original FP content, not the original BP
content. When I merged the 32-bit and 64-bit code, I used the
corresponding code from the 64-bit flow, which I believe uses the
correct offset (BPOffset) for this operation.

llvm-svn: 188741
2013-08-20 03:12:23 +00:00
Andrew Kaylor e0c8f50f3e Marking MCJIT PIC tests as XFAIL on AArch64
llvm-svn: 188740
2013-08-20 01:50:50 +00:00
Venkatraman Govindaraju f625773bca [Sparc] Use HWEncoding instead of unused Num field in Sparc register definitions. Also, correct the definitions of RETL and RET instructions.
llvm-svn: 188738
2013-08-20 01:26:14 +00:00
Andrew Kaylor ef7280c7f4 Fixing XPASSes among MCJIT PIC test on i686
llvm-svn: 188736
2013-08-20 00:37:33 +00:00
Andrew Kaylor 99974313d5 Second attempt to mark Large/PIC MCJIT test as XFAIL for PowerPC64
llvm-svn: 188735
2013-08-20 00:22:03 +00:00
Andrew Kaylor 2393389226 Marking two MCJIT PIC tests as XFAIL on Darwin
llvm-svn: 188734
2013-08-20 00:14:50 +00:00
Andrew Kaylor c4c1ff6ddd Trying again with PIC tests for MCJIT
llvm-svn: 188730
2013-08-19 23:52:53 +00:00
Hal Finkel 0c5c01aa4a Add a llvm.copysign intrinsic
This adds a llvm.copysign intrinsic; We already have Libfunc recognition for
copysign (which is turned into the FCOPYSIGN SDAG node). In order to
autovectorize calls to copysign in the loop vectorizer, we need a corresponding
intrinsic as well.

In addition to the expected changes to the language reference, the loop
vectorizer, BasicTTI, and the SDAG builder (the intrinsic is transformed into
an FCOPYSIGN node, just like the function call), this also adds FCOPYSIGN to a
few lists in LegalizeVector{Ops,Types} so that vector copysigns can be
expanded.

In TargetLoweringBase::initActions, I've made the default action for FCOPYSIGN
be Expand for vector types. This seems correct for all in-tree targets, and I
think is the right thing to do because, previously, there was no way to generate
vector-values FCOPYSIGN nodes (and most targets don't specify an action for
vector-typed FCOPYSIGN).

llvm-svn: 188728
2013-08-19 23:35:46 +00:00
Hal Finkel 1cf48ab811 Don't form PPC CTR-based loops around a copysignl call
copysign/copysignf never become function calls (because the SDAG expansion code
does not lower to the corresponding function call, but rather directly
implements the associated logic), but copysignl almost always is lowered into a
call to the requested libm functon (and, thus, might clobber CTR).

llvm-svn: 188727
2013-08-19 23:35:24 +00:00
Andrew Kaylor 4612fed911 Adding PIC support for ELF on x86_64 platforms
llvm-svn: 188726
2013-08-19 23:27:43 +00:00
Peter Collingbourne f708c87078 Introduce non-const overloads for GlobalAlias::{get,resolve}AliasedGlobal.
llvm-svn: 188725
2013-08-19 23:13:33 +00:00
Jakub Staszak b4eb6adebb Use pop_back_val() instead of both back() and pop_back().
llvm-svn: 188723
2013-08-19 22:47:55 +00:00
Matt Arsenault d79f7d9ea1 Teach InstCombine visitGetElementPtr about address spaces
llvm-svn: 188721
2013-08-19 22:17:40 +00:00
Matt Arsenault 98f34e3abe Cleanup visitGetElementPtr to make address space change easier
llvm-svn: 188720
2013-08-19 22:17:34 +00:00
Matt Arsenault 94a028aa43 commonPointerCast cleanups to make address space change easier
llvm-svn: 188719
2013-08-19 22:17:18 +00:00
Jakub Staszak fef9d0d17a Make sure that pop_back_val() result is used.
llvm-svn: 188717
2013-08-19 22:12:00 +00:00
Andrew Kaylor 28c2370602 Reverting r188709 until I can figure out the proper way to XFAIL it.
llvm-svn: 188715
2013-08-19 22:05:07 +00:00
Matt Arsenault 74742a1bb0 Fix assert with GEP ptr vector indexing structs
Also fix it calculating the wrong value. The struct index
is not a ConstantInt, so it was being interpreted as an array
index.

llvm-svn: 188713
2013-08-19 21:43:16 +00:00
Eric Christopher 574b5c8885 Use less verbose code and update comments.
llvm-svn: 188711
2013-08-19 21:41:38 +00:00
Matt Arsenault 5aeae18e9d Revert non-test parts of r188507
Re-add the inboundsless tests I didn't add originally

llvm-svn: 188710
2013-08-19 21:40:31 +00:00
Andrew Kaylor 93bf08705a Adding tests for PIC with MCJIT
llvm-svn: 188709
2013-08-19 21:08:35 +00:00