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Author SHA1 Message Date
Eli Friedman dbe2aa91b9 A couple minor README updates. 
llvm-svn: 91823
 2009-12-21 08:03:16 +00:00
Daniel Dunbar 877075a41f Remove unused variable (noticed by clang++). 
llvm-svn: 91780
 2009-12-19 18:58:49 +00:00
Daniel Dunbar 4750efc28a #if 0 out X86 disassembler for now, it is breaking the build in multiple places. 
llvm-svn: 91778
 2009-12-19 17:11:53 +00:00
Sanjiv Gupta 8ac077df57 Emit direction operand in binary insns that stores in memory. 
llvm-svn: 91777
 2009-12-19 13:52:01 +00:00
Nuno Lopes 3ed6d6003c rename dprintf to dbgpritnf, in order to fix build with glibc (which already defines dprintf in stdio.h 
llvm-svn: 91775
 2009-12-19 12:07:00 +00:00
Sanjiv Gupta 4f469974b2 1. In indirect load/store insns , the name of fsr should be emitted as INDF. 
2. include standard asmbly headers in generated asmbly.

llvm-svn: 91768
 2009-12-19 08:26:25 +00:00
Douglas Gregor 740ab38bb7 Fix a bunch of little errors that Clang complains about when its being pedantic 
llvm-svn: 91764
 2009-12-19 07:05:23 +00:00
Daniel Dunbar c745a620a2 Use memset instead of bzero, its more portable. 
llvm-svn: 91754
 2009-12-19 03:31:50 +00:00
Sean Callanan 04cc307edd Table-driven disassembler for the X86 architecture (16-, 32-, and 64-bit 
incarnations), integrated into the MC framework.  

The disassembler is table-driven, using a custom TableGen backend to 
generate hierarchical tables optimized for fast decode.  The disassembler 
consumes MemoryObjects and produces arrays of MCInsts, adhering to the 
abstract base class MCDisassembler (llvm/MC/MCDisassembler.h).

The disassembler is documented in detail in

- lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime)
- utils/TableGen/DisassemblerEmitter.cpp (table emitter)

You can test the disassembler by running llvm-mc -disassemble for i386
or x86_64 targets.  Please let me know if you encounter any problems
with it.

llvm-svn: 91749
 2009-12-19 02:59:52 +00:00
Anton Korobeynikov 148d87b0b0 Bump alignment requirements for windows targets to achieve compartibility with vcpp. 
Based on patch by Michael Beck!

llvm-svn: 91745
 2009-12-19 02:04:23 +00:00
Bill Wendling 022d18fa3f Changes from review: 
- Move DisableScheduling flag into TargetOption.h
- Move SDNodeOrdering into its own header file. Give it a minimal interface that
  doesn't conflate construction with storage.
- Move assigning the ordering into the SelectionDAGBuilder.

This isn't used yet, so there should be no functional changes.

llvm-svn: 91727
 2009-12-18 23:32:53 +00:00
Rafael Espindola b73b4fd30e Fix libstdc++ build on ARM linux and part of PR5770. 
MI was not being used but it was also not being deleted, so it was kept in the garbage list. The memory itself was freed once the function code gen was done.

Once in a while the codegen of another function would create an instruction on the same address. Adding it to the garbage group would work once, but when another pointer was added it would cause an assert as "Cache" was about to be pushed to Ts.

For a patch that make us detect problems like this earlier, take a look at

http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20091214/092758.html

With that patch we assert as soon and the new instruction is added to the garbage set.

llvm-svn: 91691
 2009-12-18 16:59:39 +00:00
Tilmann Scheller 5b2df8dcb5 Fix wrong frame pointer save offset in the 64-bit PowerPC SVR4 ABI. 
Patch contributed by Ken Werner of IBM!

llvm-svn: 91681
 2009-12-18 13:00:34 +00:00
Tilmann Scheller 79fef9349c Add support for calls through function pointers in the 64-bit PowerPC SVR4 ABI. 
Patch contributed by Ken Werner of IBM!

llvm-svn: 91680
 2009-12-18 13:00:15 +00:00
Evan Cheng 4cf30b72bf On recent Intel u-arch's, folding loads into some unary SSE instructions can 
be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.

movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0

instead of
cvtss2sd (%rdi), %xmm0

An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0

llvm-svn: 91672
 2009-12-18 07:40:29 +00:00
Eric Christopher 4c155350f1 Fix typo. 
llvm-svn: 91657
 2009-12-18 02:12:53 +00:00
Evan Cheng 3dfd04e2b7 Re-apply 91623 now that I actually know what I was trying to do. 
llvm-svn: 91655
 2009-12-18 01:59:21 +00:00
Bob Wilson 3152b0471b Handle ARM inline asm "w" constraints with 64-bit ("d") registers. 
The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types.  Radar 7457110.

llvm-svn: 91649
 2009-12-18 01:03:29 +00:00
John McCall eabfd8b155 Pass the error string directly to llvm_unreachable instead of the residual 
(0 && "error").  Rough consensus seems to be that g++ *should* be diagnosing
this because the pointer makes it not an ICE in c++03.  Everyone agrees that
the current standard is silly and null-pointer-ness should not be based on
ICE-ness.  Excellent fight scene in Act II, denouement weak, two stars.

llvm-svn: 91644
 2009-12-18 00:27:18 +00:00
Sean Callanan 04d8cb74f3 Instruction fixes, added instructions, and AsmString changes in the 
X86 instruction tables.

Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.

This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.

* X86*.td
	Removed tabs and fixed 80-line violations

* X86Instr64bit.td
	(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
		Added
	(CALL, CMOV) Added qualifiers
	(JMP) Added PC-relative jump instruction
	(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
		that it is 64-bit only (ambiguous since it has no
		REX prefix)
	(MOV) Added rr form going the other way, which is encoded
		differently
	(MOV) Changed immediates to offsets, which is more correct;
		also fixed MOV64o64a to have to a 64-bit offset
	(MOV) Fixed qualifiers
	(MOV) Added debug-register and condition-register moves
	(MOVZX) Added more forms
	(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
		(as with MOV) are encoded differently
	(ROL) Made REX.W required
	(BT) Uncommented mr form for disassembly only
	(CVT__2__) Added several missing non-intrinsic forms
	(LXADD, XCHG) Reordered operands to make more sense for
		MRMSrcMem
	(XCHG) Added register-to-register forms
	(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
	(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
		Added
* X86InstrFPStack.td
	(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
	 FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
	 FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
	 FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
	 FXRSTOR)
		Added
	(FCOM, FCOMP) Added qualifiers
	(FSTENV, FSAVE, FSTSW) Fixed opcode names
	(FNSTSW) Added implicit register operand
* X86InstrInfo.td
	(opaque512mem) Added for FXSAVE/FXRSTOR
	(offset8, offset16, offset32, offset64) Added for MOV
	(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
	 LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
	 LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
	 LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
	 CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
	 SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
	 VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
	 VMWRITE, VMXOFF, VMXON) Added
	(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
	(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
	 JGE, JLE, JG, JCXZ) Added 32-bit forms
	(MOV) Changed some immediate forms to offset forms
	(MOV) Added reversed reg-reg forms, which are encoded
		differently
	(MOV) Added debug-register and condition-register moves
	(CMOV) Added qualifiers
	(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
	(BT) Uncommented memory-register forms for disassembler
	(MOVSX, MOVZX) Added forms
	(XCHG, LXADD) Made operand order make sense for MRMSrcMem
	(XCHG) Added register-register forms
	(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
	(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
	change

* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
  qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier

llvm-svn: 91638
 2009-12-18 00:01:26 +00:00
Jeffrey Yasskin 0de0ce11d8 Revert r91623 to unbreak the buildbots. 
llvm-svn: 91632
 2009-12-17 22:44:34 +00:00
Evan Cheng e43b403c87 Remove an unused option. 
llvm-svn: 91623
 2009-12-17 21:23:58 +00:00
Chris Lattner 50272752fa finish cleaning up StructLayoutMap. 
llvm-svn: 91612
 2009-12-17 20:00:21 +00:00
Ken Dyck 798493285c In LowerEXTRACT_VECTOR_ELT, force an i32 value type for PEXTWR instead of 
incrementing the simple value type of the 16-bit type, which would give the
wrong type if an intemediate MVT (such as i24) were introduced.

llvm-svn: 91602
 2009-12-17 15:31:52 +00:00
Johnny Chen 7f30b64dce Renamed "tCMNZ" to "tCMNz" to be consistent with other similar namings. 
llvm-svn: 91571
 2009-12-16 23:36:52 +00:00
John McCall 30f2ac714b Silence a clang warning about the deprecated (but perfectly reasonable in 
context) increment-of-bool idiom.

llvm-svn: 91564
 2009-12-16 20:31:50 +00:00
Jim Grosbach 69461f50c1 Mark STREX* as earlyclobber for the success result register. 
llvm-svn: 91555
 2009-12-16 19:44:06 +00:00
Johnny Chen 466231ab92 Add encoding bits for some Thumb instructions. Plus explicitly set the top two 
bytes of Inst to 0x0000 for the benefit of the Thumb decoder.

llvm-svn: 91496
 2009-12-16 02:32:54 +00:00
Evan Cheng 1be6286028 Re-enable 91381 with fixes. 
llvm-svn: 91489
 2009-12-16 00:53:11 +00:00
John McCall 826ca5630e Every anonymous namespace is different. Caught by clang++. 
llvm-svn: 91481
 2009-12-16 00:15:28 +00:00
Jeffrey Yasskin e0d8e14e11 Change indirect-globals to use a dedicated allocIndirectGV. This lets us 
remove start/finishGVStub and the BufferState helper class from the
MachineCodeEmitter interface.  It has the side-effect of not setting the
indirect global writable and then executable on ARM, but that shouldn't be
necessary.

llvm-svn: 91464
 2009-12-15 22:42:46 +00:00
Johnny Chen c28e629c2d Added encoding bits for the Thumb ISA. Initial checkin. 
llvm-svn: 91434
 2009-12-15 17:24:14 +00:00
Evan Cheng b3032962ef Fix an encoding bug. 
llvm-svn: 91417
 2009-12-15 06:49:02 +00:00
Kenneth Uildriks 792f0913ee For fastcc on x86, let ECX be used as a return register after EAX and EDX 
llvm-svn: 91410
 2009-12-15 03:27:52 +00:00
Evan Cheng fcb5453dc7 Disable 91381 for now. It's miscompiling ARMISelDAG2DAG.cpp. 
llvm-svn: 91405
 2009-12-15 03:07:11 +00:00
Evan Cheng 0e8b9e32d1 Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's. 
llvm-svn: 91381
 2009-12-15 00:53:42 +00:00
Jim Grosbach ea8f6e31a0 nand atomic requires opposite operand ordering 
llvm-svn: 91371
 2009-12-15 00:12:35 +00:00
Dan Gohman cecad35728 Fix integer cast code to handle vector types. 
llvm-svn: 91362
 2009-12-14 23:40:38 +00:00
Johnny Chen bee6f16fed Add encoding bits "let Inst{11-4} = 0b00000000;" to BR_JTr to disambiguate 
between BR_JTr and STREXD.

llvm-svn: 91339
 2009-12-14 21:51:34 +00:00
Jim Grosbach 3974a80307 v6 sync insn copy/paste error 
llvm-svn: 91333
 2009-12-14 21:33:32 +00:00
Jim Grosbach 3c4f04112a Add ARMv6 memory and sync barrier instructions 
llvm-svn: 91329
 2009-12-14 21:24:16 +00:00
Johnny Chen acba3b0ae2 Fixed encoding bits typo of ldrexd/strexd. 
llvm-svn: 91327
 2009-12-14 21:01:46 +00:00
Jim Grosbach 57ccc19617 Thumb2 atomic operations 
llvm-svn: 91321
 2009-12-14 20:14:59 +00:00
Chris Lattner 726e452ccb fix an obvious bug found by clang++ and collapse a redundant if. 
Here's the diagnostic from clang:

/Volumes/Data/dgregor/Projects/llvm/lib/Target/CppBackend/CPPBackend.cpp:989:23: warning: 'gv' is always NULL in this context
        printConstant(gv);
                      ^
1 diagnostic generated.

llvm-svn: 91318
 2009-12-14 19:34:32 +00:00
Jim Grosbach fed3d088ce correct selection requirements for thumb2 vs. arm versions of the barrier intrinsics 
llvm-svn: 91313
 2009-12-14 19:24:11 +00:00
Jim Grosbach 20ac87de13 add Thumb2 atomic and memory barrier instruction definitions 
llvm-svn: 91310
 2009-12-14 18:56:47 +00:00
Jim Grosbach 3cdb555e0f whitespace 
llvm-svn: 91307
 2009-12-14 18:36:32 +00:00
Jim Grosbach 5e0d2a2df6 ARM memory barrier instructions are not predicable 
llvm-svn: 91305
 2009-12-14 18:31:20 +00:00
Jim Grosbach 9d6410d040 add ldrexd/strexd instructions 
llvm-svn: 91284
 2009-12-14 17:02:55 +00:00
Bill Wendling 277381f69a Whitespace changes, comment clarification. No functional changes. 
llvm-svn: 91274
 2009-12-14 06:51:19 +00:00
Jim Grosbach 8f3c70e909 atomic binary operations up to 32-bits wide. 
llvm-svn: 91260
 2009-12-14 04:22:04 +00:00
Anton Korobeynikov 45800ce646 Do not allow uninitialize access during debug printing 
llvm-svn: 91232
 2009-12-13 01:00:32 +00:00
Eli Friedman 96cf7f42b0 More info on this transformation. 
llvm-svn: 91230
 2009-12-12 23:23:43 +00:00
Eli Friedman 8eada9f580 Remove some stuff that's already implemented. Also, remove the note about 
merging x >u 5 and x <s 20 because it's impossible to implement.

llvm-svn: 91228
 2009-12-12 21:41:48 +00:00
Evan Cheng 26fdd7265b Disable r91104 for x86. It causes partial register stall which pessimize code in 32-bit. 
llvm-svn: 91223
 2009-12-12 20:03:14 +00:00
Anton Korobeynikov d8f320947f Implement variable-width shifts. 
No testcase yet - it seems we're exposing generic codegen bugs.

llvm-svn: 91221
 2009-12-12 18:55:37 +00:00
Evan Cheng 3974c8de51 Add comment about potential partial register stall. 
llvm-svn: 91220
 2009-12-12 18:55:26 +00:00
Evan Cheng 6d6eaafa8c Fix an obvious bug. No test case since LEA16r is not being used. 
llvm-svn: 91219
 2009-12-12 18:51:56 +00:00
Jim Grosbach 8f9a3ac12c Framework for atomic binary operations. The emitter for the pseudo instructions 
just issues an error for the moment. The front end won't yet generate these
intrinsics for ARM, so this is behind the scenes until complete.

llvm-svn: 91200
 2009-12-12 01:40:06 +00:00
Anton Korobeynikov e27e028cdd Lower setcc branchless, if this is profitable. 
Based on the patch by Brian Lucas!

llvm-svn: 91175
 2009-12-11 23:01:29 +00:00
Dan Gohman 1d459e4937 Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG. 
llvm-svn: 91158
 2009-12-11 21:31:27 +00:00
Jim Grosbach 22a4ea8690 memory barrier instructions by definition have side effects. This prevents the post-RA scheduler from moving them around. 
llvm-svn: 91150
 2009-12-11 20:29:53 +00:00
Anton Korobeynikov fc51282cbe Honour setHasCalls() set from isel. 
This is used in some weird cases like general dynamic TLS model.
This fixes PR5723

llvm-svn: 91144
 2009-12-11 19:39:55 +00:00
Johnny Chen 098bd1bbea Store Register Exclusive should leave the source register Inst{3-0} unspecified. 
llvm-svn: 91143
 2009-12-11 19:37:26 +00:00
Jim Grosbach afdddaed55 Update properties. 
llvm-svn: 91140
 2009-12-11 18:52:41 +00:00
Evan Cheng 766a73fb04 Add support to 3-addressify 16-bit instructions. 
llvm-svn: 91104
 2009-12-11 06:01:48 +00:00
Jim Grosbach 5c4e99fca6 Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in progress. 
llvm-svn: 91090
 2009-12-11 01:42:04 +00:00
Jim Grosbach fed78ccfb5 Add instruction encoding for DMB/DSB 
llvm-svn: 91053
 2009-12-10 18:35:32 +00:00
Jim Grosbach 53e8854443 Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics. 
llvm-svn: 91003
 2009-12-10 00:11:09 +00:00
Evan Cheng 493b882f80 Optimize splat of a scalar load into a shuffle of a vector load when it's legal. e.g. 
vector_shuffle (scalar_to_vector (i32 load (ptr + 4))), undef, <0, 0, 0, 0>
=>
vector_shuffle (v4i32 load ptr), undef, <1, 1, 1, 1>

iff ptr is 16-byte aligned (or can be made into 16-byte aligned).

llvm-svn: 90984
 2009-12-09 21:00:30 +00:00
Evan Cheng d938faff4b Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 isl lowering code. 
llvm-svn: 90925
 2009-12-09 01:53:58 +00:00
Evan Cheng f5938d5d27 Move isConsecutiveLoad to SelectionDAG. It's not target dependent and it's primary used by selectdag passes. 
llvm-svn: 90922
 2009-12-09 01:36:00 +00:00
Evan Cheng 0c2544fd6b - Support inline asm 'w' constraint for 128-bit vector types. 
- Also support the 'q' NEON registers asm code.

llvm-svn: 90894
 2009-12-08 23:06:22 +00:00
Anton Korobeynikov dd2b2f8cba Reduce (cmp 0, and_su (foo, bar)) into (bit foo, bar). This saves extra instruction. Patch inspired by Brian Lucas! 
llvm-svn: 90819
 2009-12-08 01:03:04 +00:00
Dan Gohman 9528ccdd77 Don't enable the post-RA scheduler on x86 except at -O3. In its 
current form, it is too expensive in compile time.

llvm-svn: 90781
 2009-12-07 19:04:31 +00:00
Anton Korobeynikov 24a6316aaa Some pretty-printing 
llvm-svn: 90742
 2009-12-07 02:28:41 +00:00
Anton Korobeynikov ff4ab51400 Add lowering of returnaddr and frameaddr intrinsics. Shamelessly stolen from x86 :) 
llvm-svn: 90740
 2009-12-07 02:28:10 +00:00
Anton Korobeynikov b4be8ce537 Initial codegen support for MSP430 ISRs 
llvm-svn: 90739
 2009-12-07 02:27:53 +00:00
Anton Korobeynikov 28d3c733aa Add ability to select hw multiplier mode and select appropriate libcalls. 
llvm-svn: 90737
 2009-12-07 02:27:08 +00:00
Anton Korobeynikov 75dfed4fa5 Dynamic stack realignment use of sp register as source/dest register 
in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode.
Emit the following code instead:
mov r4, sp
bic r4, r4, #15
mov sp, r4

llvm-svn: 90724
 2009-12-06 22:39:50 +00:00
Bill Wendling 29d6390249 Calling InvalidateEntry during the refinement was breaking the bootstrap. 
llvm-svn: 90656
 2009-12-05 07:59:04 +00:00
Bill Wendling fa3f115ec4 Final cleanups: 
- Privatize a typedef.
- Call the InvalidateEntry when refining a type.

llvm-svn: 90655
 2009-12-05 07:46:49 +00:00
Bill Wendling 4968774280 Inline methods which are called only once. 
llvm-svn: 90640
 2009-12-05 01:46:01 +00:00
Bill Wendling da95e13750 Refactor some code. No functionality change. 
llvm-svn: 90639
 2009-12-05 01:43:33 +00:00
Dan Gohman 047a767d74 Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of 
MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.

llvm-svn: 90634
 2009-12-05 00:44:40 +00:00
David Greene 86bafa29a3 Remove an unneeded include. 
llvm-svn: 90625
 2009-12-04 23:55:07 +00:00
David Greene 0508e435c3 Have hasLoad/StoreFrom/ToStackSlot return the relevant MachineMemOperand. 
llvm-svn: 90608
 2009-12-04 22:38:46 +00:00
Bill Wendling 4ea0d2b8ee Some code cleanup. No functionality change. 
llvm-svn: 90588
 2009-12-04 21:03:02 +00:00
Jim Grosbach 5f9f721e95 remove out of date FIXME. 
llvm-svn: 90490
 2009-12-03 21:55:01 +00:00
Chris Lattner f05330a5c8 expand note. 
llvm-svn: 90429
 2009-12-03 07:43:46 +00:00
Chris Lattner d1e4ee3c2b add a note 
llvm-svn: 90428
 2009-12-03 07:41:54 +00:00
Chris Lattner c831fac043 fix a build problem with VC++, PR5664, patch by Alp Toker! 
llvm-svn: 90419
 2009-12-03 06:58:32 +00:00
Bob Wilson 0bbd3077ce Recognize canonical forms of vector shuffles where the same vector is used for 
both source operands.  In the canonical form, the 2nd operand is changed to an
undef and the shuffle mask is adjusted to only reference elements from the 1st
operand.  Radar 7434842.

llvm-svn: 90417
 2009-12-03 06:40:55 +00:00
Bill Wendling aba7d48764 Revert r90371. It was causing build failures. 
llvm-svn: 90383
 2009-12-03 01:54:07 +00:00
Bill Wendling 693969eb35 Further improvements: refactoring code that does the same thing into one 
function, converting "dyn_cast" to "cast", asserting the correct things, and
other general cleanups.

llvm-svn: 90371
 2009-12-03 01:15:46 +00:00
Chris Lattner 765ac33a1a yay for case insensitive file systems (?) 
llvm-svn: 90370
 2009-12-03 01:10:05 +00:00
Chris Lattner 73570673de remove some dead std::ostream using code. 
llvm-svn: 90366
 2009-12-03 00:55:04 +00:00
Chris Lattner a48f44d9ee improve portability to avoid conflicting with std::next in c++'0x. 
Patch by Howard Hinnant!

llvm-svn: 90365
 2009-12-03 00:50:42 +00:00
Bill Wendling 1ed59c63e3 This initial code is meant to convert TargetData to use an AbstractTypesUser so 
that it doesn't have dangling pointers when abstract types are resolved. This
modifies it somewhat to address comments: making the "StructLayoutMap" an
anonymous structure, calling "removeAbstractTypeUser" when appropriate, and
adding asserts where helpful.

llvm-svn: 90362
 2009-12-03 00:17:12 +00:00
Jim Grosbach 2c3a6c6589 Factor the stack alignment calculations out into a target independent pass. 
No functionality change.

llvm-svn: 90336
 2009-12-02 19:30:24 +00:00
Jim Grosbach 36d4dec28a Thumb1 exception handling setjmp 
llvm-svn: 90246
 2009-12-01 18:10:36 +00:00
Johnny Chen 86fc920742 For VLDM/VSTM (Advanced SIMD), set encoding bits Inst{11-8} to 0b1011. 
llvm-svn: 90243
 2009-12-01 17:37:06 +00:00
Johnny Chen ee536b0ea4 For VMOV (immediate), make some of the encoding bits (cmode and op) unspecified. 
For VMOVv*i[16,32], op bit is don't care, and some cmode bits vary depending on
the immediate values.

Ref: Table A7-15 Modified immediate values for Advanced SIMD instructions.
llvm-svn: 90173
 2009-12-01 00:02:02 +00:00
Dan Gohman 3ee8bc9b35 Minor whitespace fixes. 
llvm-svn: 90166
 2009-11-30 23:33:53 +00:00
Dan Gohman 6f51309021 Fix a minor inconsistency. 
llvm-svn: 90165
 2009-11-30 23:33:37 +00:00
Bob Wilson 505ddaa4dc Remove isProfitableToDuplicateIndirectBranch target hook. It is profitable 
for all the processors where I have tried it, and even when it might not help
performance, the cost is quite low.  The opportunities for duplicating
indirect branches are limited by other factors so code size does not change
much due to tail duplicating indirect branches aggressively.

llvm-svn: 90144
 2009-11-30 18:35:03 +00:00
Bob Wilson c168a52627 Fix some more ARM unified syntax warnings. 
llvm-svn: 90141
 2009-11-30 17:47:19 +00:00
Mon P Wang 32f8bb9ed4 Added support to allow clients to custom widen. For X86, custom widen vectors for 
divide/remainder since these operations can trap by unroll them and adding undefs
for the resulting vector.

llvm-svn: 90108
 2009-11-30 02:42:02 +00:00
Chris Lattner 58ccf88c36 update and consolidate the load pre notes. 
llvm-svn: 90050
 2009-11-29 02:19:52 +00:00
Chris Lattner 83a4a9868f add a deadargelim note. 
llvm-svn: 90009
 2009-11-27 17:12:30 +00:00
Chris Lattner ca9e0e83b3 This testcase is actually only partially redundant, and requires 
the FIXME I added yesterday to be implemented.

llvm-svn: 90008
 2009-11-27 16:53:57 +00:00
Chris Lattner cc6d29286c this (and probably several others) are now done. 
llvm-svn: 89982
 2009-11-27 00:35:04 +00:00
Chris Lattner 9bd2136ca3 Teach memdep to phi translate bitcasts. This allows us to compile 
the example in GCC PR16799 to:

LBB1_2:                                                     ## %bb1
	movl	%eax, %eax
	subq	%rax, %rdi
	movq	%rdi, (%rcx)
	movl	(%rdi), %eax
	testl	%eax, %eax
	je	LBB1_2

instead of:

LBB1_2:                                                     ## %bb1
	movl	(%rdi), %ecx
	subq	%rcx, %rdi
	movq	%rdi, (%rax)
	cmpl	$0, (%rdi)
	je	LBB1_2

llvm-svn: 89978
 2009-11-26 23:41:07 +00:00
Chris Lattner 29bc8a91d3 Teach basicaa that x|c == x+c when the c bits of x are clear. This 
allows us to compile the example in readme.txt into:

LBB1_1:                                                     ## %bb
	movl	4(%rdx,%rax), %ecx
	movl	%ecx, %esi
	imull	(%rdx,%rax), %esi
	imull	%esi, %ecx
	movl	%esi, 8(%rdx,%rax)
	imull	%ecx, %esi
	movl	%ecx, 12(%rdx,%rax)
	movl	%esi, 16(%rdx,%rax)
	imull	%ecx, %esi
	movl	%esi, 20(%rdx,%rax)
	addq	$16, %rax
	cmpq	$4000, %rax
	jne	LBB1_1

instead of:

LBB1_1: 
	movl	(%rdx,%rax), %ecx
	imull	4(%rdx,%rax), %ecx
	movl	%ecx, 8(%rdx,%rax)
	imull	4(%rdx,%rax), %ecx
	movl	%ecx, 12(%rdx,%rax)
	imull	8(%rdx,%rax), %ecx
	movl	%ecx, 16(%rdx,%rax)
	imull	12(%rdx,%rax), %ecx
	movl	%ecx, 20(%rdx,%rax)
	addq	$16, %rax
	cmpq	$4000, %rax
	jne	LBB1_1

GCC (4.2) doesn't seem to be able to eliminate the loads in this 
testcase either, it generates:

L2:
	movl	(%rdx), %eax
	imull	4(%rdx), %eax
	movl	%eax, 8(%rdx)
	imull	4(%rdx), %eax
	movl	%eax, 12(%rdx)
	imull	8(%rdx), %eax
	movl	%eax, 16(%rdx)
	imull	12(%rdx), %eax
	movl	%eax, 20(%rdx)
	addl	$4, %ecx
	addq	$16, %rdx
	cmpl	$1002, %ecx
	jne	L2

llvm-svn: 89952
 2009-11-26 16:26:43 +00:00
Chris Lattner 12dacdd359 teach basicaa that A[i] != A[i+1]. 
llvm-svn: 89951
 2009-11-26 16:18:10 +00:00
Chris Lattner 8e09ad6f3c update some notes slightly 
llvm-svn: 89913
 2009-11-26 01:51:18 +00:00
Viktor Kutuzov 8981b3abe5 Rollback changes r89516: Added two SubtargetFeatures::AddFeatures methods, which accept a comma-separated string or already parsed command line parameters as input, and some code re-factoring to use these new methods. 
llvm-svn: 89893
 2009-11-25 22:44:18 +00:00
Bob Wilson 4419301d81 Tail duplicate indirect branches for PowerPC, too. 
With the testcase for pr3120, the "threaded interpreter" runtime decreases
from 1788 to 1413 with this change.

llvm-svn: 89877
 2009-11-25 19:57:14 +00:00
Benjamin Kramer 4cd30817d3 Avoid some possibly unsafe uses of StringRef::data(). 
llvm-svn: 89873
 2009-11-25 18:26:09 +00:00
Devang Patel 2d9caf9fe5 Use StringRef (again) in DebugInfo interface. 
llvm-svn: 89866
 2009-11-25 17:36:49 +00:00
Bob Wilson 120f729eca Based on the testcase for pr3120, running on my MacPro with Xeon processors, 
it is definitely profitable to tail duplicate indirect branches for x86.
This is likely to be true to various degrees for all modern x86 processors.

llvm-svn: 89865
 2009-11-25 17:27:53 +00:00
Bruno Cardoso Lopes 2db07581b7 Support PIC loading of constant pool entries 
llvm-svn: 89863
 2009-11-25 12:17:58 +00:00
Daniel Dunbar 900f2ce31c Sketch structure for X86 disassembler. 
llvm-svn: 89850
 2009-11-25 06:53:08 +00:00
Bruno Cardoso Lopes 2c6d498ccc Use endianess dependent offsets for load/store of doubles when 
using two swc/lwc instead of sdc/ldc.

llvm-svn: 89826
 2009-11-25 01:05:25 +00:00
Dale Johannesen e0eb336588 Fix compiler warnings. 
llvm-svn: 89824
 2009-11-25 00:58:21 +00:00
Bruno Cardoso Lopes fa2741e0d3 Only include in the callee saved regs the sub registers to avoid 
unnecessary save/restore.

llvm-svn: 89823
 2009-11-25 00:47:43 +00:00
Bruno Cardoso Lopes dce6f66cf0 Add proper emission of load/store double to stack slots for mips1 targets! 
llvm-svn: 89821
 2009-11-25 00:36:00 +00:00
Devang Patel d23ea6a33b Revert r89803. 
llvm-svn: 89819
 2009-11-25 00:31:13 +00:00
Bob Wilson d4d40670e8 Refactor target hook for tail duplication as requested by Chris. 
Make tail duplication of indirect branches much more aggressive (for targets
that indicate that it is profitable), based on further experience with
this transformation.  I compiled 3 large applications with and without
this more aggressive tail duplication and measured minimal changes in code
size.  ("size" on Darwin seems to round the text size up to the nearest
page boundary, so I can only say that any code size increase was less than
one 4k page.) Radar 7421267.

llvm-svn: 89814
 2009-11-24 23:35:49 +00:00
Dale Johannesen 5ece8f0a20 Do not store R31 into the caller's link area on PPC. 
This violates the ABI (that area is "reserved"), and
while it is safe if all code is generated with current
compilers, there is some very old code around that uses
that slot for something else, and breaks if it is stored
into.  Adjust testcases looking for current behavior.
I've verified that the stack frame size is right in all
testcases, whether it changed or not.  7311323.

llvm-svn: 89811
 2009-11-24 22:59:02 +00:00
Devang Patel 29c9b709e3 Enable debug info for ppc-darwin. 
llvm-svn: 89803
 2009-11-24 21:38:54 +00:00
Evan Cheng 184ec26fcd Enable predication of NEON instructions in Thumb2 mode. 
llvm-svn: 89748
 2009-11-24 08:06:15 +00:00
Dale Johannesen 86dcae106d Make capitalization of names starting "is" more consistent. 
No functional change.

llvm-svn: 89724
 2009-11-24 01:09:07 +00:00
Evan Cheng ece825dc4f Data type suffix must come after predicate. 
llvm-svn: 89723
 2009-11-24 01:05:23 +00:00
Anton Korobeynikov 2522908653 Materialize global addresses via movt/movw pair, this is always better 
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.

This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).

llvm-svn: 89720
 2009-11-24 00:44:37 +00:00
Jim Grosbach f890f51666 80 column violations 
llvm-svn: 89718
 2009-11-24 00:20:27 +00:00
Jeffrey Yasskin f2ad571443 * Move stub allocation inside the JITEmitter, instead of exposing a 
way for each TargetJITInfo subclass to allocate its own stubs. This
means stubs aren't as exactly-sized anymore, but it lets us get rid of
TargetJITInfo::emitFunctionStubAtAddr(), which lets ARM and PPC
support the eager JIT, fixing http://llvm.org/PR4816.

* Rename the JITEmitter's stub creation functions to describe the kind
of stub they create. So far, all of them create lazy-compilation
stubs, but they sometimes get used when far-call stubs are needed.
Fixing http://llvm.org/PR5201 will involve fixing this.

llvm-svn: 89715
 2009-11-23 23:35:19 +00:00
Dan Gohman de5dea869f Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used. 
Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.

llvm-svn: 89711
 2009-11-23 23:20:51 +00:00
Jeffrey Yasskin 19b48370fb Allow more than one stub to be being generated at the same time. 
It's probably better in the long run to replace the
indirect-GlobalVariable system. That'll be done after a subsequent
patch.

llvm-svn: 89708
 2009-11-23 22:49:00 +00:00
Evan Cheng 738a97a1db Massive refactoring of NEON instructions. Separate opcode from data size specifier suffix, move \t up stream to instruction format, and fix more 80 column violations. 
This fixes the NEON asm printing so the "predicate" field is printed between the opcode and the data type suffix.

llvm-svn: 89706
 2009-11-23 21:57:23 +00:00
Jim Grosbach dbb4140f37 move fconst[sd] to UAL. <rdar://7414913> 
llvm-svn: 89700
 2009-11-23 21:08:25 +00:00
Johnny Chen b6528d3244 Partially revert r84730 by removing N2VDup from ARMInstrFormats.td and modifying 
VDUPLND and VDUPLNQ to derive from N2V instead of N2VDup.  VDUPLND and VDUPLNQ
now expect op19_18 and op17_16 as the first two args.

llvm-svn: 89699
 2009-11-23 21:00:43 +00:00
Jim Grosbach 04c0e76772 fold immediate of a + Const into the user as a subtract if it can fit as a negated two-part immediate. 
llvm-svn: 89694
 2009-11-23 20:35:53 +00:00
Johnny Chen 5ad7416260 Revert r84572 by removing N3VImm from ARMInstrFormats.td now that we can specify 
{?,?,?,?} as op11_8 for VEXTd and VEXTq.

llvm-svn: 89693
 2009-11-23 20:09:13 +00:00
Johnny Chen e97457afbc Partially revert r89377 by removing NLdStLN class definition from 
ARMInstrFormats.td and fixing VLD[234]LN* and VST[234]LN* to derive from NLdSt
instead of NLdStLN.

llvm-svn: 89684
 2009-11-23 18:16:16 +00:00
Johnny Chen ebc60ef80c Make it clear that the index bit(s) of Vector Get Lane and Vector Set Lane 
should be left unspecified now that Bob Wilson has fixed pr5470.

llvm-svn: 89676
 2009-11-23 17:48:17 +00:00
David Goodwin 1f2457f8aa Minor itinerary fixes for FP instructions. 
llvm-svn: 89672
 2009-11-23 17:34:12 +00:00
Jim Grosbach fd963e11f5 Move default FrameReg val to getFrameIndexReference(). Otherwise, debug info can get bogus values. 
llvm-svn: 89618
 2009-11-22 20:05:32 +00:00
Jim Grosbach 90e9062e96 Generate more correct debug info for frame indices. 
llvm-svn: 89576
 2009-11-22 02:32:29 +00:00
Anton Korobeynikov abdf86d2be Minor optimization: when doing eq/ne comparions and RHS is a constant - swap operands, this will allow us to fold imm into comparison. 
llvm-svn: 89574
 2009-11-22 01:14:08 +00:00
Anton Korobeynikov 3a31644c7a Drop unsupported imm operands 
llvm-svn: 89573
 2009-11-22 01:13:54 +00:00
Anton Korobeynikov a9c7bb724a Use 2-byte alignment for functions. 4 bytes are clear overkill here. 
llvm-svn: 89572
 2009-11-22 01:13:39 +00:00
Anton Korobeynikov d099b578e4 Use semicolon as assembler comment string 
llvm-svn: 89571
 2009-11-22 01:12:49 +00:00
Jim Grosbach e09e95b35c Revert 89562. We're being sneakier than I was giving us credit for, and this 
isn't necessary.

llvm-svn: 89568
 2009-11-21 23:34:09 +00:00
Jim Grosbach 43fd822249 Darwin requires a frame pointer for all non-leaf functions to support correct 
backtraces.

llvm-svn: 89562
 2009-11-21 21:40:08 +00:00
Evan Cheng a33fc86be3 Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td. 
llvm-svn: 89542
 2009-11-21 06:21:52 +00:00
Devang Patel ed85e12da6 We are not using DBG_STOPPOINT anymore. 
llvm-svn: 89536
 2009-11-21 02:46:55 +00:00
Viktor Kutuzov 7dcca8f7fc Added two SubtargetFeatures::AddFeatures methods, which accept a comma-separated string or already parsed command line parameters as input, and some code re-factoring to use these new methods. 
llvm-svn: 89516
 2009-11-21 00:00:02 +00:00
Dan Gohman 312971513f Fix a thinko that caused spurious @GOTOFFs. 
llvm-svn: 89509
 2009-11-20 23:30:32 +00:00
Dan Gohman e14b347176 Update for new getBlockAddress signature. 
llvm-svn: 89507
 2009-11-20 23:21:00 +00:00
Dan Gohman 7a6611793f Target-independent support for TargetFlags on BlockAddress operands, 
and support for blockaddresses in x86-32 PIC mode.

llvm-svn: 89506
 2009-11-20 23:18:13 +00:00
Sean Callanan c1f532e930 Recommitting PALIGNR shift width fixes. 
Thanks to Daniel Dunbar for fixing clang intrinsics:
  http://llvm.org/viewvc/llvm-project?view=rev&revision=89499

llvm-svn: 89500
 2009-11-20 22:28:42 +00:00
Dale Johannesen 8495a506eb Remove an incorrect overaggressive optimization 
(PPC specific).

llvm-svn: 89496
 2009-11-20 22:16:40 +00:00
Sean Callanan 19d92728d0 Reverting PALIGNR fix until I figure out how this 
broke the Clang testsuite.

llvm-svn: 89495
 2009-11-20 22:09:28 +00:00
Sean Callanan fbed130173 Fixed PALIGNR to take 8-bit rotations in all cases. 
Also fixed the corresponding testcase, and the PALIGNR
  intrinsic (tested for correctness with llvm-gcc).

llvm-svn: 89491
 2009-11-20 21:40:28 +00:00
Evan Cheng bdb43a9d99 Remat VLDRD from constpool. Clean up some instruction property specifications. 
llvm-svn: 89478
 2009-11-20 19:57:15 +00:00
Jim Grosbach 6c3b71195a The verify() call of CPEIsInRange() isn't right for the assertion check of 
constant pool ranges, as CPEIsInRange() makes conservative assumptions about
the potential alignment changes from branch adjustments. The verification,
on the other hand, runs after those branch adjustments are made, so the
effects on alignment are known and already taken into account. The sanity
check in verify should check the range directly instead.

llvm-svn: 89473
 2009-11-20 19:37:38 +00:00
Jim Grosbach fc81352e3f Remove verifySizes() since it's not adding much value. 
llvm-svn: 89443
 2009-11-20 02:32:06 +00:00
Evan Cheng bbd50b0f78 Also CSE non-pic load from constant pools. 
llvm-svn: 89440
 2009-11-20 02:10:27 +00:00
Evan Cheng 81a2851bcb Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all. 
llvm-svn: 89423
 2009-11-20 00:54:03 +00:00
Eric Christopher a6380af658 Update comment to reflect instruction. 
llvm-svn: 89414
 2009-11-20 00:21:55 +00:00
Jim Grosbach b73918c42d When placing constant islands and adjusting for alignment padding, inline 
assembly can confuse things utterly, as it's assumed that instructions in
inline assembly are 4 bytes wide. For Thumb mode, that's often not true,
so the calculations for when alignment padding will be present get thrown off,
ultimately leading to out of range constant pool entry references. Making
more conservative assumptions that padding may be necessary when inline asm
is present avoids this situation.

llvm-svn: 89403
 2009-11-19 23:10:28 +00:00
Evan Cheng b6c7704a8d Refactor cmov selection code out to a separate function. No functionality change. 
llvm-svn: 89396
 2009-11-19 21:45:22 +00:00
Bill Wendling 31c74dbb10 Reverting the EH table patches. 
$ svn merge -c -89279 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r89279 into '.':
U    lib/CodeGen/AsmPrinter/DwarfException.cpp
U    lib/Target/TargetLoweringObjectFile.cpp
$ svn merge -c -89270 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r89270 into '.':
G    lib/CodeGen/AsmPrinter/DwarfException.cpp
G    lib/Target/TargetLoweringObjectFile.cpp

llvm-svn: 89379
 2009-11-19 19:21:09 +00:00
Johnny Chen b3b8209d77 Added NLdStLN which is similar to NLdSt with the exception that op7_4 is not 
fully specified at this level.  Subclasses of NLdStLN can specify selective
bit(s) for Inst{7-4}, as is done for VLD[234]LN* and VST[234]LN* inside
ARMInstrNEON.td.

llvm-svn: 89377
 2009-11-19 19:20:17 +00:00
Jim Grosbach 36a5bf82bf fix typo 
llvm-svn: 89369
 2009-11-19 18:23:19 +00:00
Dan Gohman 91431b008b Fix a typo in a comment. 
llvm-svn: 89360
 2009-11-19 16:35:11 +00:00
Evan Cheng 82adca8373 80 col violation. 
llvm-svn: 89337
 2009-11-19 08:16:50 +00:00
Evan Cheng b18525937c More consistent thumb1 asm printing. 
llvm-svn: 89328
 2009-11-19 06:57:41 +00:00
Evan Cheng 2a6c92fcb6 Shrink ldr / str [sp, imm0-1024] to 16-bit instructions. 
llvm-svn: 89326
 2009-11-19 06:32:27 +00:00
Evan Cheng 547abae38d Eliminate more * 4 in Thumb1 asm printing for consistency sake. 
llvm-svn: 89325
 2009-11-19 06:31:26 +00:00
Bruno Cardoso Lopes 4713b282ce - Add sugregister logic to handle f64=(f32,f32). 
- Support mips1 like load/store of doubles:

Instead of:
  sdc $f0, X($3)
Generate:
  swc $f0, X($3)
  swc $f1, X+4($3)

llvm-svn: 89322
 2009-11-19 06:06:13 +00:00
Bruno Cardoso Lopes 8bd87239d7 Only use small sections for non linux targets! 
llvm-svn: 89316
 2009-11-19 05:28:18 +00:00
Bill Wendling 4b384b0294 The "ReadOnlyWithRel" enum seems to apply more to what Darwin does with the EH 
exception table than DataRel.

llvm-svn: 89279
 2009-11-19 00:09:14 +00:00
Richard Osborne 3bd09434a6 Add XCore support for indirectbr / blockaddress. 
llvm-svn: 89273
 2009-11-18 23:20:42 +00:00
Bill Wendling 07e6e2c6f8 Attempt #2: 
Place the EH table in the __TEXT section on MachO. It saves space.

llvm-svn: 89270
 2009-11-18 23:18:46 +00:00
Viktor Kutuzov c3e2b6bcf5 Added getDefaultSubtargetFeatures method to SubtargetFeatures class which returns a correct feature string for given triple. 
llvm-svn: 89236
 2009-11-18 20:20:05 +00:00
David Goodwin 1fd5fdaa7b Add ARMv6 itineraries. 
llvm-svn: 89218
 2009-11-18 18:39:57 +00:00
Bob Wilson 9dea05d724 Fix a few places that were missed when we converted to unified syntax. 
llvm-svn: 89214
 2009-11-18 18:10:35 +00:00
Bob Wilson 290e9a47a9 Add a target hook to allow changing the tail duplication limit based on the 
contents of the block to be duplicated.  Use this for ARM Cortex A8/9 to
be more aggressive tail duplicating indirect branches, since it makes it
much more likely that they will be predicted in the branch target buffer.
Testcase coming soon.

llvm-svn: 89187
 2009-11-18 03:34:27 +00:00
Bill Wendling dfd8daaf61 The llvm-gcc front-end and the pass manager use two separate TargetData objects. 
This is probably not confined to *just* these two things.

Anyway, the llvm-gcc front-end may look up the structure layout information for
an abstract type. That information will be stored into a table with the FE's
TD. Instruction combine can come along and also ask for information on that
abstract type, but for a separate TD (the one associated with the pass manager).

After the type is refined, the old structure layout information in the pass
manager's TD file is out of date. If a new type is allocated in the same space
as the old-unrefined type, then the structure type information in the pass
manager's TD file will be wrong, but won't know it.

Fix this by making the TD's structure type information an abstract type user.

llvm-svn: 89176
 2009-11-18 01:03:56 +00:00
Jim Grosbach cdde77c6a3 Enable arm jumpt table adjustment. 
llvm-svn: 89143
 2009-11-17 21:24:11 +00:00
Anton Korobeynikov f24804413d Both Darwin as and GNU as violate ARM docs wrt printing of addrmode6 
alignment imm (in the same way). Fix asmprinting for non-darwin platforms.

llvm-svn: 89137
 2009-11-17 20:04:59 +00:00
Johnny Chen 14b25eb87b Set Inst{15-12} (Rd/Rt) to 0b1111 (PC) for BR_JTadd, BR_JTr, and BR_JTm to 
distinguish between them and the more generic instructions (add, mov, and ldr).

llvm-svn: 89108
 2009-11-17 17:17:50 +00:00
Evan Cheng 5392cc9d14 Re-apply 89011. It's not to be blamed. 
llvm-svn: 89081
 2009-11-17 09:51:18 +00:00
Evan Cheng 05938e819b Revert 89011. Buildbot thinks it might be breaking stuff. 
llvm-svn: 89076
 2009-11-17 09:20:28 +00:00
Jim Grosbach af1ad30a23 When moving a block for table jumps, make sure the prior block terminator 
is analyzable so it can be updated. If it's not, be safe and don't move the
block.

llvm-svn: 89022
 2009-11-17 01:21:04 +00:00
Evan Cheng d33400e636 MOV64rm should be marked isReMaterializable. 
llvm-svn: 89019
 2009-11-17 00:55:55 +00:00
Evan Cheng ce28f6f478 A few more instructions that should be marked re-materializable. 
llvm-svn: 89011
 2009-11-17 00:23:22 +00:00
Johnny Chen 18183b6d8e Set Rm bits of BX_RET to 0b1110 (R14); and set condition code bits of BRIND to 
0b1110 (ALways).  This is so that the disassembler decoder can distinguish among
BX_RET, BRIND, and BXr9.

llvm-svn: 89000
 2009-11-16 23:57:56 +00:00
Jeffrey Yasskin 10d3604a9e Make X86-64 in the Large model always emit 64-bit calls. 
The large code model is documented at
http://www.x86-64.org/documentation/abi.pdf and says that calls should
assume their target doesn't live within the 32-bit pc-relative offset
that fits in the call instruction.

To do this, we turn off the global-address->target-global-address
conversion in X86TargetLowering::LowerCall(). The first attempt at
this broke the lazy JIT because it can separate the movabs(imm->reg)
from the actual call instruction. The lazy JIT receives the address of
the movabs as a relocation and needs to record the return address from
the call; and then when that call happens, it needs to patch the
movabs with the newly-compiled target. We could thread the call
instruction into the relocation and record the movabs<->call mapping
explicitly, but that seems to require at least as much new
complication in the code generator as this change.

To fix this, we make lazy functions _always_ go through a call
stub. You'd think we'd only have to force lazy calls through a stub on
difficult platforms, but that turns out to break indirect calls
through a function pointer. The right fix for that is to distinguish
between calls and address-of operations on uncompiled functions, but
that's complex enough to leave for someone else to do.

Another attempt at this defined a new CALL64i pseudo-instruction,
which expanded to a 2-instruction sequence in the assembly output and
was special-cased in the X86CodeEmitter's emitInstruction()
function. That broke indirect calls in the same way as above.

This patch also removes a hack forcing Darwin to the small code model.
Without far-call-stubs, the small code model requires things of the
JITMemoryManager that the DefaultJITMemoryManager can't provide.

Thanks to echristo for lots of testing!

llvm-svn: 88984
 2009-11-16 22:41:33 +00:00
Evan Cheng f25ef4ffb0 - Check memoperand alignment instead of checking stack alignment. Most load / store folding instructions are not referencing spill stack slots. 
- Mark MOVUPSrm re-materializable.

llvm-svn: 88974
 2009-11-16 21:56:03 +00:00
Jim Grosbach 56ee15c162 Make the pass class name more explicit. 
llvm-svn: 88964
 2009-11-16 21:13:22 +00:00
Jim Grosbach 544b15cbc3 make pass name a bit more clear 
llvm-svn: 88961
 2009-11-16 21:03:58 +00:00
Jim Grosbach 9785e5914f Simplify thumb2 jump table adjustments. Remove unnecessary calculation and 
usage of block sizes and offsets.

llvm-svn: 88935
 2009-11-16 18:58:52 +00:00
Jim Grosbach 87b0f0d95c clarify comment 
llvm-svn: 88933
 2009-11-16 18:55:47 +00:00
Jim Grosbach 9c148c2163 back off for a bit. tracking down weirdness 
llvm-svn: 88919
 2009-11-16 17:17:48 +00:00
Jim Grosbach 47d5e333ff Analyze has to be before checking the condition, obviously. Properly construct an iterator for prior. 
llvm-svn: 88917
 2009-11-16 17:10:56 +00:00
Bruno Cardoso Lopes 5bf807688e Disable ldc1/sdc1 instructions for mips1 targets. 
llvm-svn: 88887
 2009-11-16 04:35:29 +00:00
Bruno Cardoso Lopes 537e409c58 - Fix a small bug while handling target constant pools (one param was missing). 
- Add a smarter constant pool loading, instead of:

lui $2, %hi($CPI1_0)
addiu $2, $2, %lo($CPI1_0)
lwc1 $f0, 0($2)

Generate:

lui $2, %hi($CPI1_0)
lwc1 $f0, %lo($CPI1_0)($2)

llvm-svn: 88886
 2009-11-16 04:33:42 +00:00
Jim Grosbach 01c1cae34d Detect need for autoalignment of the stack earlier to catch spills more 
conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling

llvm-svn: 88874
 2009-11-15 21:45:34 +00:00
Jim Grosbach 74ae3e5b0e set the def of the VLD1q64 properly 
llvm-svn: 88873
 2009-11-15 21:05:07 +00:00
Nick Lewycky ef4ea9a2a9 Add a complex missed optimization opportunity I came across while investigating 
bug 5438.

llvm-svn: 88855
 2009-11-15 17:51:23 +00:00
Jim Grosbach e07594df45 cleanup. 
llvm-svn: 88812
 2009-11-14 21:33:37 +00:00
Jim Grosbach 43d2108546 Cleanup flow, and only update the jump table we're analyzing when replacing a destination MBB. 
llvm-svn: 88805
 2009-11-14 20:10:18 +00:00
Richard Osborne d5f2745965 Add XCore support for arbitrary-sized aggregate returns. 
llvm-svn: 88802
 2009-11-14 19:33:35 +00:00
Anton Korobeynikov fd0c7bae2a Temporary disable the error - it seems to be too conservative. 
llvm-svn: 88800
 2009-11-14 18:01:41 +00:00
Daniel Dunbar 241d01b590 Add llvm::sys::getHostCPUName, for detecting the LLVM name for the host CPU. 
- This is an initial step towards -march=native support in Clang, and towards
   eliminating host dependencies in the targets. See PR5389.

 - Patch by Roman Divacky!

llvm-svn: 88768
 2009-11-14 10:09:12 +00:00
Sanjiv Gupta d03742a122 revert 88761 as it fails builds. 
llvm-svn: 88762
 2009-11-14 07:22:25 +00:00
Sanjiv Gupta 8f9c22646b Fix debug info crashes for PIC16. 
llvm-svn: 88761
 2009-11-14 06:19:49 +00:00
Evan Cheng 6ad7da96fe - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo. 
- If destination is a physical register and it has a subreg index, use the
  sub-register instead.
This fixes PR5423.

llvm-svn: 88745
 2009-11-14 02:55:43 +00:00
Evan Cheng 66401c90da When expanding t2STRDi8 r, r to two stores, add kill markers correctly. 
llvm-svn: 88734
 2009-11-14 01:50:00 +00:00
Jakob Stoklund Olesen ff0302489b The instruction pointer %RIP is a reserved register on x86_64. 
llvm-svn: 88705
 2009-11-13 21:56:01 +00:00
David Greene 659c1a9d78 Move DebugInfo checks into EmitComments and remove them from 
target-specific AsmPrinters.  Not all comments need DebugInfo.

Re-enable the line numbers comment test.

llvm-svn: 88697
 2009-11-13 21:34:57 +00:00
David Goodwin b9fe5d5d02 Allow target to specify regclass for which antideps will only be broken along the critical path. 
llvm-svn: 88682
 2009-11-13 19:52:48 +00:00
Bruno Cardoso Lopes a03b5b44fc Support fp64 immediate zero, this fixes only part of PR5445 
because the testcase is triggering one more bug.

llvm-svn: 88674
 2009-11-13 18:49:59 +00:00
Dale Johannesen 5f4eecf961 Adjust isConstantSplat to allow for big-endian targets. 
PPC is such a target; make it work.

llvm-svn: 87060
 2009-11-13 01:45:18 +00:00
Jim Grosbach 46a524c3e8 Block renumbering 
llvm-svn: 87056
 2009-11-13 01:19:24 +00:00
Jim Grosbach 969910b3e8 use lower case for readability 
llvm-svn: 87054
 2009-11-13 01:17:22 +00:00
David Greene 2f4c37425b Fix a bootstrap failure. 
Provide special isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE
interfaces to explicitly request checking for post-frame ptr elimination
operands.  This uses a heuristic so it isn't reliable for correctness.

llvm-svn: 87047
 2009-11-13 00:29:53 +00:00
David Greene be851acfb0 Make the MachineFunction argument of getFrameRegister const. 
This also fixes a build error.

llvm-svn: 87027
 2009-11-12 21:00:03 +00:00
David Greene 70fdd57dc1 Add hasLoadFromStackSlot and hasStoreToStackSlot to return whether a 
machine instruction loads or stores from/to a stack slot.  Unlike
isLoadFromStackSlot and isStoreFromStackSlot, the instruction may be
something other than a pure load/store (e.g. it may be an arithmetic
operation with a memory operand).  This helps AsmPrinter determine when
to print a spill/reload comment.

This is only a hint since we may not be able to figure this out in all
cases.  As such, it should not be relied upon for correctness.

Implement for X86.  Return false by default for other architectures.

llvm-svn: 87026
 2009-11-12 20:55:29 +00:00
David Greene 1fbe054450 Add a bool flag to StackObjects telling whether they reference spill 
slots.  The AsmPrinter will use this information to determine whether to
print a spill/reload comment.

Remove default argument values.  It's too easy to pass a wrong argument
value when multiple arguments have default values.  Make everything
explicit to trap bugs early.

Update all targets to adhere to the new interfaces..

llvm-svn: 87022
 2009-11-12 20:49:22 +00:00
Benjamin Kramer 68e4945c03 Add compare_lower and equals_lower methods to StringRef. Switch all users of 
StringsEqualNoCase (from StringExtras.h) to it.

llvm-svn: 87020
 2009-11-12 20:36:59 +00:00
Jim Grosbach 5d57714e6c Update TB[BH] layout optimization. Add support for moving the target block 
to directly follow the jump table. Move the layout changes to prior to any
constant island handling.

llvm-svn: 86999
 2009-11-12 17:25:07 +00:00
Evan Cheng e129dd311e Use table to separate opcode from operands. 
llvm-svn: 86965
 2009-11-12 07:16:34 +00:00
Evan Cheng 15b80e4a9f isLegalICmpImmediate should take a signed integer; code clean up. 
llvm-svn: 86964
 2009-11-12 07:13:11 +00:00
Jim Grosbach 6385ea7c4e Revert 86857. It's causing consumer-typeset to fail, and there's a better way to do it forthcoming anyway. 
llvm-svn: 86945
 2009-11-12 03:28:35 +00:00
Bruno Cardoso Lopes 626d49f684 A real solution for the first part of PR5445 
llvm-svn: 86895
 2009-11-11 23:09:33 +00:00
Evan Cheng 3d3c24a82c Add TargetLowering::isLegalICmpImmediate. It tells LSR what immediate can be folded into target icmp instructions. 
llvm-svn: 86858
 2009-11-11 19:05:52 +00:00
Jim Grosbach d576d66d91 Do jump table adjustment before constant island allocation 
llvm-svn: 86857
 2009-11-11 19:04:24 +00:00
Dan Gohman 9fd22f68f2 Set isBarrier = 1 on return instructions, as they are control barriers. 
llvm-svn: 86851
 2009-11-11 18:11:07 +00:00
Dan Gohman d2a0f80ede Use a tab in INT3's asm string, for consistency. 
llvm-svn: 86850
 2009-11-11 18:07:16 +00:00
Chris Lattner 7a09964e81 another const prop failure. 
llvm-svn: 86848
 2009-11-11 17:54:02 +00:00
Chris Lattner 539bdf0487 add a note 
llvm-svn: 86847
 2009-11-11 17:51:27 +00:00
Jim Grosbach 8d92ec45c7 The TBB and TBH instructions for Thumb2 are really handy for jump tables, but 
can only branch forward. To best take advantage of them, we'd like to adjust
the basic blocks around a bit when reasonable. This patch puts basics in place
to do that, with a super-simple algorithm for backwards jump table targets that
creates a new branch after the jump table which branches backwards. Real
heuristics for reordering blocks or other modifications rather than inserting
branches will follow.

llvm-svn: 86791
 2009-11-11 02:47:19 +00:00
Daniel Dunbar bc299f0092 llvm-gcc/clang don't (won't?) need this hack. 
llvm-svn: 86769
 2009-11-11 00:28:38 +00:00
Chris Lattner 0169fd7c62 add a note 
llvm-svn: 86756
 2009-11-10 23:47:45 +00:00
Chris Lattner 8ff26038ef I did this a week or two ago 
llvm-svn: 86754
 2009-11-10 23:40:49 +00:00
Dan Gohman de8d418ac3 Don't mark conditional branch instructions as control barriers. 
llvm-svn: 86732
 2009-11-10 22:16:57 +00:00