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233 Commits

Author SHA1 Message Date
Evan Cheng dd7f566597 Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects. 
llvm-svn: 104111
 2010-05-19 06:07:03 +00:00
Evan Cheng 79efd71962 Mark some pattern-less instructions as neverHasSideEffects. 
llvm-svn: 103683
 2010-05-13 00:16:46 +00:00
Anton Korobeynikov 2063705d91 Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :( 
llvm-svn: 100650
 2010-04-07 18:20:02 +00:00
Anton Korobeynikov c1e7a6feac FCONST{S,D} behaves the same way as FP unary instructions. This is true for both A8 and A9. 
llvm-svn: 100649
 2010-04-07 18:19:56 +00:00
Anton Korobeynikov 4c1da0f82a Add new itin classes for FP16 <-> FP32 conversions and make uise of them for A9. 
llvm-svn: 100647
 2010-04-07 18:19:46 +00:00
Jim Grosbach 34de7768bf Make the use of the vmla and vmls VFP instructions controllable via cmd line. 
Preliminary testing shows significant performance wins by not using these
instructions.

llvm-svn: 99436
 2010-03-24 22:31:46 +00:00
Bob Wilson 2497d85c9e Revert the rest of 98679. 
--- Reverse-merging r98679 into 'lib/Target/ARM/ARMInstrVFP.td':
U    lib/Target/ARM/ARMInstrVFP.td

llvm-svn: 99049
 2010-03-20 06:34:02 +00:00
Bob Wilson e4191e719b Revert this change, since it was causing ARM performance regressions. 
--- Reverse-merging r98889 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMISelLowering.h
U    lib/Target/ARM/ARMInstrInfo.td
U    lib/Target/ARM/ARMInstrVFP.td
U    lib/Target/ARM/ARMISelLowering.cpp
U    lib/Target/ARM/ARMInstrFormats.td

llvm-svn: 99010
 2010-03-19 22:51:32 +00:00
Anton Korobeynikov f11aa9e7b4 Get rid of target-specific fp <-> int nodes when still I'm here. 
llvm-svn: 98889
 2010-03-18 22:35:45 +00:00
Anton Korobeynikov 64578d5599 Get rid of target-specific nodes for fp16 <-> fp32 conversion. 
llvm-svn: 98888
 2010-03-18 22:35:37 +00:00
Johnny Chen 71ab18bdd5 Disambiguate the *_UPD and * variants by specifying the writeback flag as 1. 
This is for the disassembly work.

There are cases where this is not possible, for example, A8.6.53 LDM Encoding T1.
In such case, we'll use an adhoc approach to deduce the Opcode programmatically.

llvm-svn: 98679
 2010-03-16 21:25:05 +00:00
Bob Wilson 466d1e3dc2 Remove redundant writeback flag in ARM addressing mode 5. 
llvm-svn: 98648
 2010-03-16 18:38:09 +00:00
Anton Korobeynikov d7fece38fc Add codegen support for FP16 on ARM 
llvm-svn: 98502
 2010-03-14 18:42:31 +00:00
Bob Wilson f1e8f7ff7d Attempt to appease the arm-linux buildbot by fixing the JIT encodings for new 
base register updating load/store-multiple instructions.

llvm-svn: 98427
 2010-03-13 07:34:35 +00:00
Bob Wilson 947f04bad0 Change ARM ld/st multiple instructions to have variant instructions for 
writebacks to the address register.  This gets rid of the hack that the
first register on the list was the magic writeback register operand.  There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand.  The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other.  This also fixes Radar 7495976 and should help the verifier work
better for ARM code.

There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.

llvm-svn: 98409
 2010-03-13 01:08:20 +00:00
Chris Lattner b8a7427636 fix a bunch of partially ambiguous patterns on ARM. As an 
example, this:

(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))

is ambiguous because DPR contains both f64 and v2f32.  tblgen
currently accidentally picks f64 because it's first in the 
regclass.

llvm-svn: 97955
 2010-03-08 18:51:21 +00:00
Dan Gohman 8c5d683aa9 The mayHaveSideEffects flag is no longer used. 
llvm-svn: 97348
 2010-02-27 23:47:46 +00:00
Johnny Chen 2588efd071 Added VCVT (between floating-point and fixed-point, VFP) for disassembly. 
A8.6.297

llvm-svn: 95885
 2010-02-11 18:17:16 +00:00
Johnny Chen b618f66c5f Added VMRS/VMSR for disassembly only. 
A8.6.335 & A8.6.336

llvm-svn: 95703
 2010-02-09 22:35:38 +00:00
Johnny Chen 64e0ae8dd4 Added vcvtb/vcvtt (between half-precision and single-precision, VFP). 
For disassembly only.

A8.6.300

llvm-svn: 95669
 2010-02-09 17:21:56 +00:00
Johnny Chen 9e60686a83 Add VCVTR (between floating-point and integer, VFP) for disassembly purpose. 
The 'R' suffix means the to-integer operations use the rounding mode specified
by the FPSCR, encoded as Inst{7} = 0.

A8.6.295

llvm-svn: 95584
 2010-02-08 22:02:41 +00:00
Johnny Chen beb1238a85 Add VCMP (VFP floating-point compare without 'E' bit set) for disassembly purpose. 
llvm-svn: 95560
 2010-02-08 19:41:48 +00:00
Johnny Chen c7e606f132 Added VMOVRRS/VMOVSRR to ARMInstrVFP.td for disassembly purpose. 
A8.6.331 VMOV (between two ARM core registers and two single-precision registers)

llvm-svn: 95548
 2010-02-08 17:26:09 +00:00
Johnny Chen a778db9a91 VMOVRRD and VMOVDRR both have Inst{7-6} = 0b00. 
llvm-svn: 95397
 2010-02-05 18:04:58 +00:00
Johnny Chen 34a6afc68d Modified encoding bits specification for VFP instructions. In particular, the D 
bit (Inst{22}) and the M bit (Inst{5}) should be left unspecified.  For binary
format instructions, Inst{6} and Inst{4} need to specified for proper decodings.

llvm-svn: 94855
 2010-01-29 23:21:10 +00:00
Evan Cheng ece825dc4f Data type suffix must come after predicate. 
llvm-svn: 89723
 2009-11-24 01:05:23 +00:00
Jim Grosbach dbb4140f37 move fconst[sd] to UAL. <rdar://7414913> 
llvm-svn: 89700
 2009-11-23 21:08:25 +00:00
Evan Cheng bdb43a9d99 Remat VLDRD from constpool. Clean up some instruction property specifications. 
llvm-svn: 89478
 2009-11-20 19:57:15 +00:00
Jim Grosbach 969910b3e8 use lower case for readability 
llvm-svn: 87054
 2009-11-13 01:17:22 +00:00
Evan Cheng e6548f4106 Add a comment. 
llvm-svn: 86706
 2009-11-10 19:44:56 +00:00
Jim Grosbach ad95414c26 Work around assembler not recognizing #0.0 form immediate for vmcp 
llvm-svn: 86548
 2009-11-09 15:27:51 +00:00
Jim Grosbach d7cf55cd0e Use Unified Assembly Syntax for the ARM backend. 
llvm-svn: 86494
 2009-11-09 00:11:35 +00:00
Evan Cheng 6203c6868f fconsts and fconstd are obviously re-materializable. 
llvm-svn: 85410
 2009-10-28 18:19:56 +00:00
Evan Cheng 4a609f3cef Use fconsts and fconstd to materialize small fp constants. 
llvm-svn: 85362
 2009-10-28 01:44:26 +00:00
Evan Cheng 538984c1c3 Now VFP instructions. 
llvm-svn: 85186
 2009-10-27 00:20:49 +00:00
Evan Cheng 1b2b64f618 Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple, 
ld / st pairs, etc.

llvm-svn: 83197
 2009-10-01 08:22:27 +00:00
Evan Cheng 3bbc6c3ae6 Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions. 
llvm-svn: 83191
 2009-10-01 01:33:39 +00:00
David Goodwin bea6848f9d Finish scheduling itineraries for NEON. 
llvm-svn: 82788
 2009-09-25 18:38:29 +00:00
David Goodwin 5090273367 Add Cortex-A8 VFP model. 
llvm-svn: 82483
 2009-09-21 20:52:17 +00:00
David Goodwin 85b5b027f7 Use NEON for single-precision int<->FP conversions. 
llvm-svn: 78604
 2009-08-10 22:17:39 +00:00
David Goodwin b062c236c5 Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary. 
llvm-svn: 78321
 2009-08-06 16:52:47 +00:00
David Goodwin 30bf625ac2 Add NEON single-precision FP support for fabs and fneg. 
llvm-svn: 78101
 2009-08-04 20:39:05 +00:00
David Goodwin a3839bc6c0 Match common pattern for FNMAC. Add NEON SP support. 
llvm-svn: 78085
 2009-08-04 18:44:29 +00:00
David Goodwin 3b9c52c5c1 Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations. 
llvm-svn: 78081
 2009-08-04 17:53:06 +00:00
Evan Cheng d214b72962 Model fpscr to prevent fcmped / fcmpezs etc from being deleted. 
llvm-svn: 76390
 2009-07-20 02:12:31 +00:00
David Goodwin 81cdd21dcb Predicate VFP instructions on HasVFP2 instead of IsARM. This allows VFP instructions with thumb-2. 
llvm-svn: 75254
 2009-07-10 17:03:29 +00:00
Evan Cheng d93b5b672f Mark some pattern-less instructions as neverHasSideEffects. 
llvm-svn: 73252
 2009-06-12 20:46:18 +00:00
Evan Cheng a52c3b4b8b Fix a 80 col. violation. 
llvm-svn: 60901
 2008-12-11 22:02:02 +00:00
Dan Gohman 69cc2cbbff Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning. 
llvm-svn: 60487
 2008-12-03 18:15:48 +00:00
Evan Cheng 9c205bf03c Fix fuitos encoding. 
llvm-svn: 59344
 2008-11-15 00:40:57 +00:00
Evan Cheng 320902bcfc fsub{d|s} encoding bugs. 
llvm-svn: 59234
 2008-11-13 07:59:48 +00:00
Evan Cheng af644b50b4 Consolidate formats; fix FCMPED etc. encodings. 
llvm-svn: 59107
 2008-11-12 07:18:38 +00:00
Evan Cheng 4b6c7efbde Fix VFP conversion instruction encodings. 
llvm-svn: 59104
 2008-11-12 06:41:41 +00:00
Evan Cheng a0e2f26320 Fix encoding of single-precision VFP registers. 
llvm-svn: 59102
 2008-11-12 02:19:38 +00:00
Evan Cheng 97ccab888a Fix FMDRR encoding. 
llvm-svn: 59088
 2008-11-11 22:46:12 +00:00
Evan Cheng 8cbbcb1f2f Encode VFP load / store instructions. 
llvm-svn: 59084
 2008-11-11 21:48:44 +00:00
Evan Cheng 38c9a14a88 Encode VFP conversion instructions. 
llvm-svn: 59074
 2008-11-11 19:40:26 +00:00
Evan Cheng ac2af2fdb2 Encode VFP arithmetic instructions. 
llvm-svn: 59016
 2008-11-11 02:11:05 +00:00
Evan Cheng 47b546d75f Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug. 
llvm-svn: 58800
 2008-11-06 08:47:38 +00:00
Jim Grosbach a7cd7bc353 udpate header comment: s/VP/VFP/ 
llvm-svn: 56126
 2008-09-11 21:41:29 +00:00
Evan Cheng 0e7b00d79f Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF. 
llvm-svn: 48380
 2008-03-15 00:03:38 +00:00
Chris Lattner 9a249b0ce5 rename SDTRet -> SDTNone. 
Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.

llvm-svn: 46017
 2008-01-15 22:02:54 +00:00
Chris Lattner 94de7bc3aa get def use info more correct. 
llvm-svn: 45821
 2008-01-10 05:12:37 +00:00
Evan Cheng 7250120177 Only mark instructions that load a single value without extension as isSimpleLoad = 1. 
llvm-svn: 45727
 2008-01-07 23:56:57 +00:00
Chris Lattner a4ce4f6987 rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. 
llvm-svn: 45667
 2008-01-06 23:38:27 +00:00
Chris Lattner 10324d0175 rename isStore -> mayStore to more accurately reflect what it captures. 
llvm-svn: 45656
 2008-01-06 08:36:04 +00:00
Chris Lattner f4d55ec4e8 remove explicit isStore flags that are now inferrable. 
llvm-svn: 45653
 2008-01-06 05:55:01 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Evan Cheng 6e68381e02 Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled. 
llvm-svn: 44960
 2007-12-12 23:12:09 +00:00
Evan Cheng 3e18e504ae Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. 
llvm-svn: 41863
 2007-09-11 19:55:27 +00:00
Evan Cheng f7c6effc44 Initial JIT support for ARM by Raul Fernandes Herbster. 
llvm-svn: 40887
 2007-08-07 01:37:15 +00:00
Evan Cheng 94b5a80b93 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
 2007-07-19 01:14:50 +00:00
Evan Cheng 9d41b311fb Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. 
llvm-svn: 38501
 2007-07-10 18:08:01 +00:00
Evan Cheng 881248c4e1 No need for ccop anymore. 
llvm-svn: 37965
 2007-07-06 23:34:09 +00:00
Evan Cheng aa3b8014bd Each ARM use predicate operand is now made up of two components. The new component is the CPSR register. 
llvm-svn: 37895
 2007-07-05 07:13:32 +00:00
Evan Cheng e8c3cbf971 Mark these instructions clobbersPred. They modify the condition code register. 
llvm-svn: 37468
 2007-06-06 10:17:05 +00:00
Evan Cheng 19eeee41ca For VFP2 fldm, fstm instructions, the condition code is printed after the address mode and size specifier. e.g. fstmiaseq, not fstmeqias. 
llvm-svn: 37351
 2007-05-29 23:34:19 +00:00
Evan Cheng 0f7cbe8370 Add PredicateOperand to all ARM instructions that have the condition field. 
llvm-svn: 37066
 2007-05-15 01:29:07 +00:00
Evan Cheng 9c031c0ddf Switch BCC, MOVCCr, etc. to PredicateOperand. 
llvm-svn: 36948
 2007-05-08 21:08:43 +00:00
Evan Cheng d37c23745f This is no longer needed after enabling the DAG combiner xform. 
llvm-svn: 36909
 2007-05-07 21:29:41 +00:00
Dale Johannesen 89200ce0f0 Evan's patch to avoid FPreg->intreg copy for cvt; store to mem 
llvm-svn: 36693
 2007-05-03 20:54:42 +00:00
Chris Lattner 1c1082133c match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.ll 
llvm-svn: 36660
 2007-05-03 00:32:00 +00:00
Evan Cheng 10043e215b ARM backend contribution from Apple. 
llvm-svn: 33353
 2007-01-19 07:51:42 +00:00