283418fbb6
[AVX512] Add patterns for any-extending a mask that use the def of KMOVW/KMOVB without going through an EXTRACT_SUBREG and a MOVZX.
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llvm-svn: 273253
2016-06-21 07:37:32 +00:00
9038aa3001
[AVX512] Use update_llc_test_checks.py to regenerate a test in preparation for a future commit.
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llvm-svn: 273252
2016-06-21 07:37:27 +00:00
fba562004b
[X86][AVX512] Lower broadcast sub vector to vector inrtrinsics
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lower broadcast<type>x<vector> to shuffles.
there are two cases:
1.src is 128 bits and dest is 512 bits: in this case we will lower it to shuffle with imm = 0.
2.src is 256 bit and dest is 512 bits: in this case we will lower it to shuffle with imm = 01000100b (0x44) that way we will broadcast the 256bit source: ymm[0,1,2,3] => zmm[0,1,2,3,0,1,2,3] then it will mask it with the passthru value (in case it's mask op).
Differential Revision: http://reviews.llvm.org/D15790
llvm-svn: 256490
2015-12-28 08:26:26 +00:00
756c289dd8
AVX512: Change VPMOVB2M DAG lowering , use CVT2MASK node instead TRUNCATE.
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Fix TRUNCATE lowering vector to vector i1, use LSB and not MSB.
Implement VPMOVB/W/D/Q2M intrinsic.
Differential Revision: http://reviews.llvm.org/D15675
llvm-svn: 256470
2015-12-27 13:56:16 +00:00
268f6f53c5
AVX512: VPMOVM2B/W/D/Q intrinsic implementation.
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Differential Revision: http://reviews.llvm.org//D15747
llvm-svn: 256364
2015-12-24 07:11:53 +00:00
7c2c9fd243
AVX-512: Fixed COPY_TO_REGCLASS for mask registers
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Copying one mask register to another under BW should be done with kmovq instruction, otherwise we can loose some bits.
Copying 8 bits under DQ may be done with kmovb.
Differential Revision: http://reviews.llvm.org/D14812
llvm-svn: 253563
2015-11-19 13:13:00 +00:00
fa798a9dbb
AVX512: Implemented encoding and intrinsics for VBROADCASTI32x2 and VBROADCASTF32x2 instructions.
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Differential Revision: http://reviews.llvm.org/D14216
llvm-svn: 251781
2015-11-02 07:39:36 +00:00
696e8e0bb7
[X86][AVX512DQ] add scalar fpclass
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Differential Revision: http://reviews.llvm.org/D13769
llvm-svn: 250650
2015-10-18 11:04:38 +00:00
572bbceecc
[X86][AVX512DQ] Add fpclass instruction
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Differential Revision: http://reviews.llvm.org/D12931
llvm-svn: 248115
2015-09-20 08:46:07 +00:00
0ede3cbb5c
AVX512: Implement instructions encoding, lowering and intrinsics
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vinserti64x4, vinserti64x2, vinserti32x8, vinserti32x4, vinsertf64x4, vinsertf64x2, vinsertf32x8, vinsertf32x4
Added tests for encoding, lowering and intrinsics.
Differential Revision: http://reviews.llvm.org/D11893
llvm-svn: 248111
2015-09-20 06:52:42 +00:00
7f69a99c54
AVX512: Implemented encoding and intrinsics for
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vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4
Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D11802
llvm-svn: 247276
2015-09-10 12:54:54 +00:00
db7ea86bf4
Revert "AVX512: Implemented encoding and intrinsics for vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4 Added tests for intrinsics and encoding."
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This reverts commit r247149, as it was breaking numerous buildbots of varied architectures.
llvm-svn: 247177
2015-09-09 19:44:40 +00:00
ac29a82921
AVX512: Implemented encoding and intrinsics for
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vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4
Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D11802
llvm-svn: 247149
2015-09-09 14:35:09 +00:00
a5b2e5e2a7
[X86][AVX512] add reduce/range/scalef/rndScale
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include encoding and intrinsics
Differential Revision: http://reviews.llvm.org/D11222
llvm-svn: 242896
2015-07-22 12:00:43 +00:00
a26f10ce18
AVX-512: Added intrinsics for VCVT* instructions.
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All SKX forms. All VCVT instructions for float/double/int/long types.
Differential Revision: http://reviews.llvm.org/D11343
llvm-svn: 242877
2015-07-22 08:56:00 +00:00
Craig Topper