Commit Graph

288441 Commits

Author SHA1 Message Date
Heejin Ahn d20d0648ed [DAGCombiner] Fix a case of 1 in non-splat vector pow2 divisor
Summary:
D42479 (rL329525) enabled SDIV combine for pow2 non-splat vector
dividers. But when there is a 1 in a vector, the instruction sequence to
be generated involves shifting a value by the number of its bit widths,
which is undefined
(c64f4dbfe3/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (L6000-L6006)).

Especially, in architectures that do not support vector instructions,
each of element in a vector will be computed separately using scalar
operations, and then the resulting value will be undef for '1' values
in a vector.

(All 1's vector is fine; only vectors mixed with 1 and others will be
affected.)

Reviewers: RKSimon, jgravelle-google

Subscribers: jfb, dschuff, sbc100, jgravelle-google, llvm-commits

Differential Revision: https://reviews.llvm.org/D46161

llvm-svn: 331092
2018-04-27 22:23:11 +00:00
Craig Topper d656410293 [X86] Make the STTNI flag intrinsics use the flags from pcmpestrm/pcmpistrm if the mask instrinsics are also used in the same basic block.
Summary:
Previously the flag intrinsics always used the index instructions even if a mask instruction also exists.

To fix fix this I've created a single ISD node type that returns index, mask, and flags. The SelectionDAG CSE process will merge all flavors of intrinsics with the same inputs to a s ingle node. Then during isel we just have to look at which results are used to know what instruction to generate. If both mask and index are used we'll need to emit two instructions. But for all other cases we can emit a single instruction.

Since I had to do manual isel anyway, I've removed the pseudo instructions and custom inserter code that was working around tablegen limitations with multiple implicit defs.

I've also renamed the recently added sse42.ll test case to sttni.ll since it focuses on that subset of the sse4.2 instructions.

Reviewers: chandlerc, RKSimon, spatel

Reviewed By: chandlerc

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46202

llvm-svn: 331091
2018-04-27 22:15:33 +00:00
Adrian Prantl 4b542c6e64 Fix a bug that prevents global variables from having a DW_OP_deref.
For local variables the first DW_OP_deref is consumed by turning the
location kind into a memeory location, but that only makes sense for
values that are in a register to begin with, which cannot happen for
global variables that are attached to a symbol.

rdar://problem/39741860

This reapplies r330970 after fixing an uncovered bug in r331086 and
working around the situation caused by it.

llvm-svn: 331090
2018-04-27 22:05:31 +00:00
Artem Dergachev befce13328 [analyzer] ObjCAutoreleaseWrite: Support a few more APIs and fix warning text.
API list and improved warning text composed by Devin Coughlin.

llvm-svn: 331089
2018-04-27 22:00:51 +00:00
Reid Kleckner efc0f8cbdc [FastISel] Actually enable local value sinking by default
llvm-svn: 331088
2018-04-27 21:51:25 +00:00
Reid Kleckner a28e767f06 [FastISel] Fix local value sinking algorithmic complexity
Now local value sinking only scans and numbers instructions added
between the current flush point and the last flush point. This ensures
that ISel is overall linear in the size of the BB.

Fixes PR37010 and re-enables local value sinking by default.

llvm-svn: 331087
2018-04-27 21:48:51 +00:00
Adrian Prantl 210a29de7b Fix a bug in GlobalOpt's handling of DIExpressions.
This patch adds support for fragment expressions
TryToShrinkGlobalToBoolean() which were previously just dropped.

Thanks to Reid Kleckner for providing me a reproducer!

llvm-svn: 331086
2018-04-27 21:41:36 +00:00
Roman Lebedev 6959b8e76f [PatternMatch] Stabilize the matching order of commutative matchers
Summary:
Currently, we
1. match `LHS` matcher to the `first` operand of binary operator,
2. and then match `RHS` matcher to the `second` operand of binary operator.
If that does not match, we swap the `LHS` and `RHS` matchers:
1. match `RHS` matcher to the `first` operand of binary operator,
2. and then match `LHS` matcher to the `second` operand of binary operator.

This works ok.
But it complicates writing of commutative matchers, where one would like to match
(`m_Value()`) the value on one side, and use (`m_Specific()`) it on the other side.

This is additionally complicated by the fact that `m_Specific()` stores the `Value *`,
not `Value **`, so it won't work at all out of the box.

The last problem is trivially solved by adding a new `m_c_Specific()` that stores the
`Value **`, not `Value *`. I'm choosing to add a new matcher, not change the existing
one because i guess all the current users are ok with existing behavior,
and this additional pointer indirection may have performance drawbacks.
Also, i'm storing pointer, not reference, because for some mysterious-to-me reason
it did not work with the reference.

The first one appears trivial, too.
Currently, we
1. match `LHS` matcher to the `first` operand of binary operator,
2. and then match `RHS` matcher to the `second` operand of binary operator.
If that does not match, we swap the ~~`LHS` and `RHS` matchers~~ **operands**:
1. match ~~`RHS`~~ **`LHS`** matcher to the ~~`first`~~ **`second`** operand of binary operator,
2. and then match ~~`LHS`~~ **`RHS`** matcher to the ~~`second`~ **`first`** operand of binary operator.

Surprisingly, `$ ninja check-llvm` still passes with this.
But i expect the bots will disagree..

The motivational unittest is included.
I'd like to use this in D45664.

Reviewers: spatel, craig.topper, arsenm, RKSimon

Reviewed By: craig.topper

Subscribers: xbolva00, wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D45828

llvm-svn: 331085
2018-04-27 21:23:20 +00:00
Simon Pilgrim 8ee7d01dcf [X86] Merge some x87 instruction instregex single matches. NFCI.
llvm-svn: 331084
2018-04-27 21:14:19 +00:00
Sanjay Patel 2677038cc0 [Reassociate] add a test with debug info; NFC
As suggested in D45842 
(although still not sure if we're going to advance that),
we must invalidate references to instructions that have
been recycled (operands were changed, so result is different).

llvm-svn: 331083
2018-04-27 21:14:15 +00:00
Greg Clayton 27a0e10a3e Fix build bots after r331049 broke them.
llvm-svn: 331082
2018-04-27 21:10:07 +00:00
Daniel Sanders 4f246999d9 Attempt to fix remaining build failures after r331071 by changing the tuple to a struct
Some of the bots were failing in a different way to the others. These were
unable to compare tuples. Fix this by changing to a struct, thereby avoiding
the quirks of tuples.

llvm-svn: 331081
2018-04-27 21:03:27 +00:00
Philip Reames 5a6482450a [LICM] Reduce nesting with an early return [NFC]
llvm-svn: 331080
2018-04-27 20:58:30 +00:00
Philip Reames e4ec473b3f [MustExecute/LICM] Special case first instruction in throwing header
We currently have a hard to solve analysis problem around the order of instructions within a potentially throwing block.  We can't cheaply determine whether a given instruction is before the first potential throw in the block.  While we're working on that in the background, special case the first instruction within the header.

why this particular special case?  Well, headers are guaranteed to execute if the loop does, and it turns out we tend to produce this form in practice.

In a follow on patch, I tend to extend LICM with an alternate approach which works for any instruction in the header before the first throw, but this is the best I can come up with other users of the analysis (such as store promotion.)

Note: I can't show the difference in the analysis result since we're ORing in the expensive instruction walk used by SCEV.  Using the full walk is not suitable for a general solution.
llvm-svn: 331079
2018-04-27 20:44:01 +00:00
Vlad Tsyrklevich 201a1086cf ELFObjectWriter: Allow one unique symver per symbol
Summary:
Only allow a single unique .symver alias per symbol. This matches the
behavior of gas. I noticed that we ignored multiple mismatched symver
directives looking at https://reviews.llvm.org/D45798

Reviewers: pcc, tejohnson, espindola

Reviewed By: pcc

Subscribers: emaste, arichardson, llvm-commits, kcc

Differential Revision: https://reviews.llvm.org/D45845

llvm-svn: 331078
2018-04-27 20:32:34 +00:00
Nico Weber 6bc635ef56 Revert r329698 (and r329702).
Speculative. ClangMoveTests started failing on
http://lab.llvm.org:8011/builders/clang-x64-ninja-win7/builds/9958
after this change. I can't reproduce on my machine, let's see
if it was due to this change.

llvm-svn: 331077
2018-04-27 20:29:57 +00:00
Daniel Neilson a19ee7d7b6 [LV] Common duplicate vector load/store address calculation (NFC)
Summary:
Commoning some obviously copy/paste code in
InnerLoopVectorizer::vectorizeMemoryInstruction

llvm-svn: 331076
2018-04-27 20:29:18 +00:00
Rafael Espindola bd4d2acb11 Don't create a temporary DenseMap for each input .eh_frame.
These maps are small, but we are creating an destroying one for each
input .eh_frame.

This patch reduces the total memory allocation from 765.54MB to
749.19MB. The peak is still the same: 563.7MB.

llvm-svn: 331075
2018-04-27 20:19:28 +00:00
Daniel Sanders a05e8d3e68 Attempt to fix build failure after r331071 using std::make_tuple
llvm-svn: 331074
2018-04-27 20:17:44 +00:00
Frederic Riss 60b94c296e [debugserver] Fix the G packet handling.
Of course r331004 needed a counterpart on the write side.

llvm-svn: 331073
2018-04-27 19:59:42 +00:00
Jun Bum Lim 9e3e14b5f9 [PostRASink] extend the live-in check for all aliased registers
Extend the live-in check for all aliased registers so that we can
allow sinking Copy instructions when only implicit def is in successor's
live-in.

llvm-svn: 331072
2018-04-27 19:59:20 +00:00
Daniel Sanders 27fe8a5011 [globalisel][legalizerinfo] Add support for legalization based on the MachineMemOperand
Summary:
Currently only the memory size is supported but others can be added as
needed.

narrowScalar for G_LOAD and G_STORE now correctly update the
MachineMemOperand and will refuse to legalize atomics since those need more
careful expansions to maintain atomicity.

Reviewers: ab, aditya_nandakumar, bogner, rtereshin, aemerson, javed.absar

Reviewed By: aemerson

Subscribers: aemerson, rovka, kristof.beyls, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D45466

llvm-svn: 331071
2018-04-27 19:48:53 +00:00
Paul Semel 3a8a56b8b7 [llvm-objcopy] Add --weaken-symbol (-W) option
llvm-svn: 331070
2018-04-27 19:16:27 +00:00
Nico Weber 1865df4996 s/LLVM_ON_WIN32/_WIN32/, clang
LLVM_ON_WIN32 is set exactly with MSVC and MinGW (but not Cygwin) in
HandleLLVMOptions.cmake, which is where _WIN32 defined too.  Just use the
default macro instead of a reinvented one.

See thread "Replacing LLVM_ON_WIN32 with just _WIN32" on llvm-dev and cfe-dev.
No intended behavior change.

llvm-svn: 331069
2018-04-27 19:11:14 +00:00
Paul Semel ee5be798da [llvm-objcopy] Add --globalize-symbol option
llvm-svn: 331068
2018-04-27 19:09:44 +00:00
Ben Hamilton 345f8739d8 [clang-format/ObjC] Use getIdentifierInfo() instead of tok::identifier
Summary:
Previously, we checked tokens for `tok::identifier` to see if they
were identifiers inside an Objective-C selector.

However, this missed C++ keywords like `new` and `delete`.

To fix this, this diff uses `getIdentifierInfo()` to find
identifiers or keywords inside Objective-C selectors.

Test Plan: New tests added. Ran tests with:
  % make -j16 FormatTests && ./tools/clang/unittests/Format/FormatTests

Reviewers: djasper, jolesiak

Reviewed By: djasper

Subscribers: klimek, cfe-commits

Differential Revision: https://reviews.llvm.org/D46143

llvm-svn: 331067
2018-04-27 18:51:12 +00:00
Jun Bum Lim 47aece1344 [CodeGen] Use RegUnits to track register aliases (NFC)
Summary: Use RegUnits to track register aliases in PostRASink and AArch64LoadStoreOptimizer.

Reviewers: thegameg, mcrosier, gberry, qcolombet, sebpop, MatzeB, t.p.northover, javed.absar

Reviewed By: thegameg, sebpop

Subscribers: javed.absar, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D45695

llvm-svn: 331066
2018-04-27 18:44:37 +00:00
Simon Pilgrim 8a937e00d8 [X86] Split WriteFBlend/WriteFVarBlend/WriteFVarShuffle into XMM and YMM/ZMM scheduler classes
This removes all the WriteFBlend/WriteFVarBlend InstRW overrides - some WriteFVarShuffle remain to be fixed.

llvm-svn: 331065
2018-04-27 18:19:48 +00:00
Rafael Espindola f1652d4c60 Split .eh_frame sections in parellel.
We can now split them in the same spot we split merge sections.

llvm-svn: 331064
2018-04-27 18:17:36 +00:00
Bruno Cardoso Lopes fbff2fafb3 [Modules][ObjC] ASTReader should add protocols for class extensions
During deserialization clang is currently missing the merging of
protocols into the canonical interface for the class extension.

This merging only currently happens during parsing and should also
be considered during deserialization.

rdar://problem/38724303

llvm-svn: 331063
2018-04-27 18:01:23 +00:00
Mark Searles a6322924e6 [AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained.
Differential Revision: https://reviews.llvm.org/D46154

llvm-svn: 331062
2018-04-27 17:59:15 +00:00
Philip Reames de5a1da2d2 [GuardWidening] Add some clarifying comments about heuristics [NFC]
llvm-svn: 331061
2018-04-27 17:41:37 +00:00
Philip Reames 9258e9d190 [LoopGuardWidening] Split out a loop pass version of GuardWidening
The idea is to have a pass which performs the same transformation as GuardWidening, but can be run within a loop pass manager without disrupting the pass manager structure.  As demonstrated by the test case, this doesn't quite get there because of issues with post dom, but it gives a good step in the right direction.  the motivation is purely to reduce compile time since we can now preserve locality during the loop walk.

This patch only includes a legacy pass.  A follow up will add a new style pass as well.

llvm-svn: 331060
2018-04-27 17:29:10 +00:00
Sanjay Patel f6d595bd44 [docs] add fp-cast-overflow-workaround options to release notes
llvm-svn: 331059
2018-04-27 16:33:35 +00:00
Rafael Espindola 9bf1006278 Split merge sections early.
Now that getSectionPiece is fast (uses a hash) it is probably OK to
split merge sections early.

The reason I want to do this is to split eh_frame sections in the same
place.

This does mean that we have to decompress early. Given that the only
compressed sections are debug info, I don't think we are missing much.

It is a small improvement: 0.5% on the geometric mean.

llvm-svn: 331058
2018-04-27 16:29:57 +00:00
Sanjay Patel c1ecbf261f [docs] more dashes
llvm-svn: 331057
2018-04-27 16:24:39 +00:00
Sanjay Patel cee47befe4 [docs] add -ffp-cast-overflow-workaround to the release notes
This option was added with:
D46135
rL331041
...copying the text from UsersManual.rst for more exposure.

llvm-svn: 331056
2018-04-27 16:21:22 +00:00
Nirav Dave 6b01b88012 [MC] Undo spurious commit added into r331052.
llvm-svn: 331055
2018-04-27 16:16:06 +00:00
Simon Pilgrim c3c767bf50 [X86] Split WriteFHadd into XMM and YMM/ZMM scheduler classes
This removes all the HADD/HSUB PS/PD InstRW overrides.

llvm-svn: 331054
2018-04-27 16:11:57 +00:00
Stuart Brady a38f573ad0 Test commit removing trailing whitespace
llvm-svn: 331053
2018-04-27 16:11:56 +00:00
Nirav Dave 38b4b54a2c [MC] Provide default value for IsResolved.
llvm-svn: 331052
2018-04-27 16:11:24 +00:00
Simon Pilgrim b2aa89c909 [X86][AVX] Split WriteFLogic into XMM and YMM/ZMM scheduler classes
This removes all the AND/ANDN/OR/XOR PS/PD InstRW overrides.

llvm-svn: 331051
2018-04-27 15:50:33 +00:00
Simon Dardis e3c3c5a7a7 [mips] Analyze and provide selection patterns microMIPSR6 branches
These branches were previously unanalyzable and unselectable. Add them and
recognize how to generate their inverses.

Reviewers: smaksimovic, atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D46113

llvm-svn: 331050
2018-04-27 15:49:49 +00:00
Greg Clayton 776cd7ad44 Always normalize FileSpec paths.
Always normalizing lldb_private::FileSpec paths will help us get a consistent results from comparisons when setting breakpoints and when looking for source files. This also removes a lot of complexity from the comparison routines. Modified the DWARF line table parser to use the normalized compile unit directory if needed.

Differential Revision: https://reviews.llvm.org/D45977

llvm-svn: 331049
2018-04-27 15:45:58 +00:00
Nirav Dave 1b5533c9e8 [MC] Modify MCAsmStreamer to always build MCAssembler. NFCI.
llvm-svn: 331048
2018-04-27 15:45:54 +00:00
Nirav Dave 8728e097df [MC] Allow MCAssembler to be constructed without all subcomponents. NFCI.
llvm-svn: 331047
2018-04-27 15:45:27 +00:00
Zaara Syeda 82dd99e08e [PPC64] Add offset to local entry point when calling functions without plt
PPC64 V2 ABI describes two entry points to a function. The global entry point
sets up the TOC base pointer. When calling a local function, the call should
branch to the local entry point rather than the global entry point.
Section 3.4.1 describes using the 3 most significant bits of the st_other
field to find out how many instructions there are between the local and global
entry point. This patch adds the correct offset required to branch to the local
entry point of a function.

Differential Revision: https://reviews.llvm.org/D45729

llvm-svn: 331046
2018-04-27 15:41:19 +00:00
Rui Ueyama 50bf643cfb Do not set RequiresNullTerminator. NFC.
When reading object files, we don't need '\0' at end of each file.

llvm-svn: 331045
2018-04-27 15:32:04 +00:00
Francis Visoiu Mistrih c855e92ca9 [AArch64] Place the first ldp at the end when ReverseCSRRestoreSeq is true
Put the first ldp at the end, so that the load-store optimizer can run
and merge the ldp and the add into a post-index ldp.

This didn't work in case no frame was needed and resulted in code size
regressions.

llvm-svn: 331044
2018-04-27 15:30:54 +00:00
Frederic Riss ffb8d8711c Mark test as @skipIfOutOfTreeDebugserver
This test will currently fail for people using the system debugserver.

llvm-svn: 331043
2018-04-27 15:30:09 +00:00