Commit Graph

20760 Commits

Author SHA1 Message Date
Elena Demikhovsky fb44980b41 Optimization for SIGN_EXTEND operation on AVX.
Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32
extensions.

llvm-svn: 149600
2012-02-02 09:10:43 +00:00
Francois Pichet 26f302d568 Unbreak the MSVC build.
llvm-svn: 149599
2012-02-02 08:36:09 +00:00
Lang Hames 0269caafa6 Set EFLAGS correctly in EmitLoweredSelect on X86.
llvm-svn: 149597
2012-02-02 07:48:37 +00:00
Akira Hatanaka 961883c1cf Set the correct stack pointer register.
llvm-svn: 149585
2012-02-02 03:17:04 +00:00
Akira Hatanaka f029537e68 Expand EHSELECTION and EHSELECTION nodes. Set the correct exception pointer and
selector registers.
 

llvm-svn: 149584
2012-02-02 03:13:40 +00:00
Akira Hatanaka d9fef17749 Add DWARF numbers of 64-bit registers.
llvm-svn: 149583
2012-02-02 02:56:14 +00:00
Rafael Espindola 77295818f0 Fix the cmake build
llvm-svn: 149561
2012-02-01 23:40:51 +00:00
Andrew Trick 8523b16ff5 Instruction scheduling itinerary for Intel Atom.
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.

Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.

Adds a test to verify that the scheduler is working.

Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.

Patch by Preston Gurd!

llvm-svn: 149558
2012-02-01 23:20:51 +00:00
Jakob Stoklund Olesen c7024a48db Move ARM subreg index compositions to the SubRegIndex itself.
llvm-svn: 149557
2012-02-01 23:16:43 +00:00
Mon P Wang 9f05206659 Avoid creating an extract element to an illegal type after LegalizeTypes has run.
llvm-svn: 149548
2012-02-01 22:15:20 +00:00
Andrew Trick d06df96a7c VLIW specific scheduler framework that utilizes deterministic finite automaton (DFA).
This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling.

Patch by Sergei Larin!

llvm-svn: 149547
2012-02-01 22:13:57 +00:00
Chad Rosier e273cb08c4 Tidy up.
llvm-svn: 149521
2012-02-01 18:45:51 +00:00
Elena Demikhovsky 824eed70a6 Passing AVX 256-bit structures in Win64 was wrong.
Fixed Win64 calling conventions.

llvm-svn: 149494
2012-02-01 10:46:14 +00:00
Elena Demikhovsky 34cca175ab Shortened code in shuffle masks
llvm-svn: 149493
2012-02-01 10:33:05 +00:00
Elena Demikhovsky 0e48c70ba7 Optimization for "truncate" operation on AVX.
Truncating v4i64 -> v4i32 and v8i32 -> v8i16 may be done with set of shuffles.

llvm-svn: 149485
2012-02-01 07:56:44 +00:00
Stepan Dyatkovskiy 513aaa5691 SwitchInst refactoring.
The purpose of refactoring is to hide operand roles from SwitchInst user (programmer). If you want to play with operands directly, probably you will need lower level methods than SwitchInst ones (TerminatorInst or may be User). After this patch we can reorganize SwitchInst operands and successors as we want.

What was done:

1. Changed semantics of index inside the getCaseValue method:
getCaseValue(0) means "get first case", not a condition. Use getCondition() if you want to resolve the condition. I propose don't mix SwitchInst case indexing with low level indexing (TI successors indexing, User's operands indexing), since it may be dangerous.
2. By the same reason findCaseValue(ConstantInt*) returns actual number of case value. 0 means first case, not default. If there is no case with given value, ErrorIndex will returned.
3. Added getCaseSuccessor method. I propose to avoid usage of TerminatorInst::getSuccessor if you want to resolve case successor BB. Use getCaseSuccessor instead, since internal SwitchInst organization of operands/successors is hidden and may be changed in any moment.
4. Added resolveSuccessorIndex and resolveCaseIndex. The main purpose of these methods is to see how case successors are really mapped in TerminatorInst.
4.1 "resolveSuccessorIndex" was created if you need to level down from SwitchInst to TerminatorInst. It returns TerminatorInst's successor index for given case successor.
4.2 "resolveCaseIndex" converts low level successors index to case index that curresponds to the given successor.

Note: There are also related compatability fix patches for dragonegg, klee, llvm-gcc-4.0, llvm-gcc-4.2, safecode, clang.
llvm-svn: 149481
2012-02-01 07:49:51 +00:00
Craig Topper 9cdb8bdf04 Don't create VBROADCAST nodes if any nodes use the chain result from the load. Fixes PR11900.
llvm-svn: 149478
2012-02-01 06:51:58 +00:00
Argyrios Kyrtzidis 17c981a45b Revert Chris' commits up to r149348 that started causing VMCoreTests unit test to fail.
These are:

r149348
r149351
r149352
r149354
r149356
r149357
r149361
r149362
r149364
r149365

llvm-svn: 149470
2012-02-01 04:51:17 +00:00
Jim Grosbach a2147ce313 Tidy up. One more return type mismatch fix.
llvm-svn: 149452
2012-01-31 23:51:09 +00:00
Jim Grosbach 44091c2f10 Refactor loop for better readability.
Excellent suggestion from Ben Kramer.

llvm-svn: 149417
2012-01-31 20:56:55 +00:00
Jim Grosbach b4d3a6af97 Add explanatory comment.
llvm-svn: 149416
2012-01-31 20:34:53 +00:00
Devang Patel a173ee56fd Add assembler dialect attribute in asm parser which lets target specific asm parser change dialect on the fly.
llvm-svn: 149396
2012-01-31 18:14:05 +00:00
Craig Topper b85e40f738 Remove pcmpgt/pcmpeq intrinsics as clang is not using them.
llvm-svn: 149367
2012-01-31 06:52:44 +00:00
Chris Lattner 8ea967d050 with recent changes, ConstantArray is never a "string". Remove the associated
methods and constant fold the clients to false.

llvm-svn: 149362
2012-01-31 06:05:00 +00:00
Chris Lattner 3a565d6241 use the right accessor for ConstantDataArray.
llvm-svn: 149342
2012-01-31 03:16:39 +00:00
Evan Cheng 4e7992eeba PR11834: Use macros which are defined on Windows. Patch by Marina Yatsina.
llvm-svn: 149294
2012-01-30 23:10:32 +00:00
Devang Patel 7cdb2ff6b5 Intel syntax. Adjust special code, used to recognize cmp<comparison code>{ss,sd,ps,pd}, for intel syntax.
llvm-svn: 149291
2012-01-30 22:47:12 +00:00
Devang Patel 9a9bb5c5db Intel syntax. Support .intel_syntax directive.
llvm-svn: 149270
2012-01-30 20:02:42 +00:00
Benjamin Kramer 396c590818 Fix refacto.
llvm-svn: 149269
2012-01-30 20:01:35 +00:00
Douglas Gregor e577cfe172 Eliminate narrowing conversion in initializer list, to make C++11 happy
llvm-svn: 149254
2012-01-30 16:57:18 +00:00
Benjamin Kramer 20af25f47b X86: Simplify shuffle mask generation code.
llvm-svn: 149248
2012-01-30 15:16:21 +00:00
Craig Topper 516cba3380 Fix pattern for memory form of PSHUFD for use with FP vectors to remove bitcast to an integer vector that normal code wouldn't have. Also remove bitcasts from code that turns splat vector loads into a shuffle as it was making the broken pattern necessary.
llvm-svn: 149232
2012-01-30 07:50:31 +00:00
Craig Topper ca29bcfc10 Move some XOP patterns into instruction definition. Replae VPCMOV intrinsic patterns with custom lowering to a target specific nodes.
llvm-svn: 149216
2012-01-30 01:10:15 +00:00
Anton Korobeynikov d0c46550fe Cleanups for EABI standard functions
llvm-svn: 149195
2012-01-29 09:11:50 +00:00
Anton Korobeynikov 1b42e64280 Use base AAPCS for varargs functions even for AAPCS-VFP CC
llvm-svn: 149194
2012-01-29 09:06:09 +00:00
Bob Wilson de0c335560 Add a note about a potential optimization for clz/ctz patterns for ARM
(and other targets).

llvm-svn: 149182
2012-01-28 18:30:07 +00:00
James Molloy b47489d4ef Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM and MIPS ELF backends.
Fixes PR11877

llvm-svn: 149180
2012-01-28 15:58:32 +00:00
Devang Patel 63fe5697f4 Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320]
llvm-svn: 149142
2012-01-27 19:48:28 +00:00
Craig Topper 5639e9e8fb Move some patterns back near their instructions and use AddedComplexity to fix priority. Merge some patterns into their instruction definition.
llvm-svn: 149122
2012-01-27 07:09:40 +00:00
Jim Grosbach 8f28dbdde5 Keep source location information for X86 MCFixup's.
llvm-svn: 149106
2012-01-27 00:51:27 +00:00
Jim Grosbach 20275a8577 Better user diagnostics for more ARM MachO relocation errors.
llvm-svn: 149102
2012-01-27 00:37:12 +00:00
Jim Grosbach b591277c4a Better diagnostic for malformed .org assembly directive.
Provide source line number information.

llvm-svn: 149101
2012-01-27 00:37:08 +00:00
Jim Grosbach 5e5eabb5ab Keep source information, if available, around for ARM Fixups.
Adjust an example MachObjectWriter diagnostic to use the information
to issue a better message.

Before:
LLVM ERROR: unknown ARM fixup kind!

After:
x.s:6:5: error: unsupported relocation on symbol
    beq bar
    ^

rdar://9800182

llvm-svn: 149093
2012-01-26 23:20:15 +00:00
Jakob Stoklund Olesen fc9dce25f7 Handle call-clobbered ymm registers on Win64.
The Win64 calling convention has xmm6-15 as callee-saved while still
clobbering all ymm registers.

Add a YMM_HI_6_15 pseudo-register that aliases the clobbered part of the
ymm registers, and mark that as call-clobbered.  This allows live xmm
registers across calls.

This hack wouldn't be necessary with RegisterMask operands representing
the call clobbers, but they are not quite operational yet.

llvm-svn: 149088
2012-01-26 22:59:28 +00:00
Jim Grosbach c8f2b7877b Tidy up. Fix mismatched return types for error handling.
llvm-svn: 149062
2012-01-26 15:56:45 +00:00
James Molloy 6685c08e5f Add support for the R_ARM_TARGET1 relocation, which should be given to relocations applied to all C++ constructors and destructors.
This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against.

llvm-svn: 149057
2012-01-26 09:25:43 +00:00
Victor Umansky 5f29b0e57b Fix for the following bug in AVX codegen for double-to-int conversions:
.	"fptosi" and "fptoui" IR instructions are defined with round-to-zero rounding mode.
.	Currently for AVX mode for <4xdouble> and <8xdouble>  the "VCVTPD2DQ.128" and "VCVTPD2DQ.256" instructions are selected (for .fp_to_sint. DAG node operation ) by AVX codegen. However they use round-to-nearest-even rounding mode.
.	Consequently, the conversion produces incorrect numbers.
 
The fix is to replace selection of VCVTPD2DQ instructions with VCVTTPD2DQ instructions. The latter use truncate (i.e. round-to-zero) rounding mode. 
As .fp_to_sint. DAG node operation is used only for lowering of  "fptosi" and "fptoui" IR instructions, the fix in X86InstrSSE.td definition file doesn.t have an impact on other LLVM flows.
 
The patch includes changes in the .td file, LIT test for the changes and a fix in a legacy LIT test (which produced asm code conflicting with LLVN IR spec). 

llvm-svn: 149056
2012-01-26 08:51:39 +00:00
Craig Topper 86e44bc829 Add HasXOP predicate check covering a bunch of XOP intrinsic patterns.
llvm-svn: 149054
2012-01-26 07:51:55 +00:00
Craig Topper 1c0e22f57a Fix AVX vs SSE patterns ordering issue for VPCMPESTRM and VPCMPISTRM.
llvm-svn: 149053
2012-01-26 07:31:30 +00:00
Craig Topper b91760eff8 Remove some more patterns by custom lowering intrinsics to target specific nodes.
llvm-svn: 149052
2012-01-26 07:18:03 +00:00
Anton Korobeynikov 7722a2d4e3 Properly emit ctors / dtors with priorities into desired sections
and let linker handle the rest.

This finally fixes PR5329

llvm-svn: 148990
2012-01-25 22:24:19 +00:00
Jim Grosbach 82f76d1275 ARM assemly parsing and validation of IT instruction.
"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."

PR11853

llvm-svn: 148969
2012-01-25 19:52:01 +00:00
Chris Lattner 33633a90a0 fix a bug I introduced in r148929, this is not a splat!
Thanks to Eli for noticing.

llvm-svn: 148947
2012-01-25 09:56:22 +00:00
Craig Topper 7834900950 Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specific nodes so we can remove the isel patterns.
llvm-svn: 148933
2012-01-25 06:43:11 +00:00
Chris Lattner 47a86bdbe2 use ConstantVector::getSplat in a few places.
llvm-svn: 148929
2012-01-25 06:02:56 +00:00
Craig Topper ce4f9c5668 Custom lower phadd and phsub intrinsics to target specific nodes. Remove the patterns that are no longer necessary.
llvm-svn: 148927
2012-01-25 05:37:32 +00:00
Craig Topper 5bcf070e68 Remove AVX 256-bit unaligned load intrinsics. 128-bit versions had been removed a while ago.
llvm-svn: 148922
2012-01-25 04:42:03 +00:00
Akira Hatanaka 012f041bce Mark 64-bit register RA_64 unused too.
llvm-svn: 148918
2012-01-25 04:19:22 +00:00
Akira Hatanaka 01d3c42f90 Modify MipsFrameLowering::emitPrologue and emitEpilogue.
- Use MipsAnalyzeImmediate to expand immediates that do not fit in 16-bit.
- Change the types of variables so that they are sufficiently large to handle
  64-bit pointers.
- Emit instructions to set register $28 in a function prologue after
  instructions which store callee-saved registers have been emitted. 
 

llvm-svn: 148917
2012-01-25 04:12:04 +00:00
Akira Hatanaka d1d4b3efcf Modify MipsRegisterInfo::eliminateFrameIndex to use MipsAnalyzeImmediate to
expand offsets that do not fit in the 16-bit immediate field of load and store
instructions. Also change the types of variables so that they are sufficiently
large to handle 64-bit pointers.

llvm-svn: 148916
2012-01-25 03:55:10 +00:00
Craig Topper 3ad5bc019a Merge intrinsic pattern and no pattern versions of VCVTSD2SI intruction definitions. Matches non-AVX version of same instructions.
llvm-svn: 148914
2012-01-25 03:52:09 +00:00
NAKAMURA Takumi 6c421ea484 MipsAnalyzeImmediate.h: Fix to add DataTypes.h for msvc.
inttypes.h is not supplied in msvc.

llvm-svn: 148912
2012-01-25 03:34:41 +00:00
NAKAMURA Takumi 96a21dcea3 Target/Mips: Unbreak CMake build.
llvm-svn: 148909
2012-01-25 03:15:46 +00:00
Akira Hatanaka 86d5fadd57 Lower 64-bit immediates using MipsAnalyzeImmediate that has just been added.
Add a test case to show fewer instructions are needed to load an immediate
with the new way of loading immediates.

llvm-svn: 148908
2012-01-25 03:01:35 +00:00
Akira Hatanaka ff36fd3de3 Add class MipsAnalyzeImmediate which comes up with an instruction sequence to
load an immediate. 

llvm-svn: 148900
2012-01-25 01:43:36 +00:00
Jim Grosbach 086cbfac7d NEON VLD4(all lanes) assembly parsing and encoding.
llvm-svn: 148884
2012-01-25 00:01:08 +00:00
Jim Grosbach ccb6d55dae Tidy up. Rename VLD4DUP patterns for consistency.
llvm-svn: 148883
2012-01-24 23:47:07 +00:00
Jim Grosbach b78403ce48 NEON VLD3(all lanes) assembly parsing and encoding.
llvm-svn: 148882
2012-01-24 23:47:04 +00:00
Akira Hatanaka d7970f9e4b Sign-extend 32-bit integer arguments when they are passed in 64-bit registers,
which is what N32/64 does.

llvm-svn: 148875
2012-01-24 23:18:43 +00:00
Akira Hatanaka 7e6c195c11 Pass CCState by reference.
llvm-svn: 148871
2012-01-24 22:07:36 +00:00
Akira Hatanaka 77dbd786c8 Pattern for f32 to i64 conversion.
llvm-svn: 148869
2012-01-24 22:05:25 +00:00
Devang Patel a410ed3ced Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax.
llvm-svn: 148864
2012-01-24 21:43:36 +00:00
Akira Hatanaka 9f7ec1538f 64-bit sign extension in register instructions.
llvm-svn: 148862
2012-01-24 21:41:09 +00:00
Jim Grosbach 8e2722cdb0 NEON VST4(one lane) assembly parsing and encoding.
llvm-svn: 148836
2012-01-24 18:53:13 +00:00
Owen Anderson d845d9d9e9 Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand.
llvm-svn: 148833
2012-01-24 18:37:29 +00:00
Jim Grosbach 14952a0e32 NEON VLD4(one lane) assembly parsing and encoding.
llvm-svn: 148832
2012-01-24 18:37:25 +00:00
Jim Grosbach 3cfef8d467 NEON Two-operand assembly aliases for VSRA.
llvm-svn: 148821
2012-01-24 17:55:36 +00:00
Jim Grosbach 7ae12cc546 NEON Two-operand assembly aliases for VSLI.
llvm-svn: 148819
2012-01-24 17:49:15 +00:00
Jim Grosbach 7b6f0f67aa NEON Two-operand assembly aliases for VSRI.
llvm-svn: 148818
2012-01-24 17:46:58 +00:00
Jim Grosbach 681db34eae NEON add correct predicates for some asm aliases.
llvm-svn: 148815
2012-01-24 17:23:29 +00:00
Chris Lattner 139822fc83 C++, CBE, and TLOF support for ConstantDataSequential
llvm-svn: 148805
2012-01-24 14:17:05 +00:00
Elena Demikhovsky 0b0c5d8c4c ZERO_EXTEND operation is optimized for AVX.
v8i16 -> v8i32, v4i32 -> v4i64 - used vpunpck* instructions.

llvm-svn: 148803
2012-01-24 13:54:13 +00:00
Anton Korobeynikov 3cad0c21ed Use correct register class for am2offset register operands.
This pacifies machine verifier

llvm-svn: 148782
2012-01-24 04:58:56 +00:00
Craig Topper 0d8e67aebd Add comments near load pattern fragments indicating that all integer vector loads are promoted to v2i64 or v4i64 so that no one tries to reintroduce pattern fragments for other types.
llvm-svn: 148771
2012-01-24 03:03:17 +00:00
Jim Grosbach da70eac268 NEON VST4(multiple 4 element structures) assembly parsing.
llvm-svn: 148764
2012-01-24 00:58:13 +00:00
Jim Grosbach ed561fc850 NEON VLD4(multiple 4 element structures) assembly parsing.
llvm-svn: 148762
2012-01-24 00:43:17 +00:00
Jim Grosbach 1e946a4f91 Tidy up. Remove some vertical space for readability.
llvm-svn: 148761
2012-01-24 00:43:12 +00:00
Chandler Carruth ed975232bc Revert r148686 (and r148694, a fix to it) due to a serious layering
violation -- MC cannot depend on CodeGen.

Specifically, the MCTargetDesc component of each target is actually
a subcomponent of the MC library. As such, it cannot depend on the
target-independent code generator, because MC itself cannot depend on
the target-independent code generator. This change moved a flag from the
ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in
ARMException.cpp, leaving behind an 'extern' to refer back to it. That
layering order isn't viable givin the constraints outlined above.
Commandline flags are designed to be static specifically to avoid these
types of bugs.

Fixing this is likely going to require some non-trivial refactoring.

llvm-svn: 148759
2012-01-24 00:30:17 +00:00
Jim Grosbach 17bacab475 Fix typo.
llvm-svn: 148757
2012-01-24 00:12:39 +00:00
Jim Grosbach d3d36d9315 NEON VST3(single element from one lane) assembly parsing.
llvm-svn: 148755
2012-01-24 00:07:41 +00:00
Devang Patel eba7d3dba9 Fix typo.
llvm-svn: 148751
2012-01-23 23:56:33 +00:00
Jim Grosbach 1a74724fc9 NEON VST3(multiple 3-element structures) assembly parsing.
llvm-svn: 148748
2012-01-23 23:45:44 +00:00
Jim Grosbach ac2af3ffab NEON VLD3(multiple 3-element structures) assembly parsing.
llvm-svn: 148745
2012-01-23 23:20:46 +00:00
Anton Korobeynikov 820417af07 Add missed mayStore flag to STREXD / t2STREXD
llvm-svn: 148742
2012-01-23 22:57:52 +00:00
Devang Patel cf893a437e Intel syntax: Robustify parsing of memory operand's displacement experssion.
llvm-svn: 148737
2012-01-23 22:35:25 +00:00
Jim Grosbach a8b444b08b NEON VLD3 lane-indexed assembly parsing and encoding.
llvm-svn: 148734
2012-01-23 21:53:26 +00:00
Devang Patel e660fdd953 Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]
llvm-svn: 148721
2012-01-23 20:20:06 +00:00
Jim Grosbach d28ef9ac46 Simplify some NEON assembly pseudo definitions.
Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.

llvm-svn: 148718
2012-01-23 19:39:08 +00:00
Devang Patel 880bc1644b Intel syntax: Parse segment registers.
llvm-svn: 148712
2012-01-23 18:31:58 +00:00
NAKAMURA Takumi 28ea8f523b ARMAsmPrinter.cpp: Try to fix up r148686. EnableARMEHABI was also here.
llvm-svn: 148694
2012-01-23 09:14:42 +00:00
Craig Topper edd1d0acfc Custom lower PCMPEQ/PCMPGT intrinsics to target specific nodes and remove the intrinsic patterns.
llvm-svn: 148687
2012-01-23 08:18:28 +00:00
Evgeniy Stepanov 482cdc4ebd An option to selectively enable parts of ARM EHABI support.
This change adds an new value to the --arm-enable-ehabi option that
disables emitting unwinding descriptors. This mode gives a working
backtrace() without the (currently broken) exception support.

llvm-svn: 148686
2012-01-23 07:57:39 +00:00
Craig Topper 6b90c5d03e Update more places to use target specific nodes for vector shifts instead of intrinsics.
llvm-svn: 148685
2012-01-23 06:46:22 +00:00
Craig Topper 5e80db4e4f Custom lower vector shift intrinsics to target specific nodes and remove the patterns that are no longer needed.
llvm-svn: 148684
2012-01-23 06:16:53 +00:00
Craig Topper 20c98df340 Remove pattern fragments for v32i8, v16i16, v8i32, v16i8, v8i16, and v4i32 loads. All integer vector loads are promoted to v2i64 or v4i64 so these pattern fragments can never match. Fix or remove patterns that used these fragments.
llvm-svn: 148672
2012-01-23 00:06:44 +00:00
Craig Topper 0b7ad76bd0 Combine X86 CMPPD and CMPPS node types. Simplifies selection code and pattern matching.
llvm-svn: 148670
2012-01-22 23:36:02 +00:00
Craig Topper bd4884371b Merge PCMPEQB/PCMPEQW/PCMPEQD/PCMPEQQ and PCMPGTB/PCMPGTW/PCMPGTD/PCMPGTQ X86 ISD node types into only two node types. Simplifying opcode selection and pattern matching.
llvm-svn: 148667
2012-01-22 22:42:16 +00:00
Nicolas Geoffray e197d943f3 Use Attributes::None instead of 0 after r148553 change on Attributes from unsigned to their own class.
llvm-svn: 148665
2012-01-22 20:05:26 +00:00
Craig Topper 094626414d Add target specific ISD node types for SSE/AVX vector shuffle instructions and change all the code that used to create intrinsic nodes to create the new nodes instead.
llvm-svn: 148664
2012-01-22 19:15:14 +00:00
Anton Korobeynikov 5482b9f535 Add fused multiple+add instructions from VFPv4.
Patch by Ana Pazos!

llvm-svn: 148658
2012-01-22 12:07:33 +00:00
Craig Topper a4ed5246d8 Make code a little less verbose.
llvm-svn: 148651
2012-01-22 03:07:48 +00:00
Craig Topper cb3433cd58 Remove unused X86 ISD node type defines.
llvm-svn: 148644
2012-01-22 01:15:56 +00:00
Craig Topper 123adfa0f3 Move some vector shift patterns into their instruction definitions.
llvm-svn: 148643
2012-01-22 00:41:20 +00:00
Craig Topper dcaa5fbd08 Add memory patterns for some of the fp<->integer conversion instructions. Fold some patterns into instruction definitions.
llvm-svn: 148641
2012-01-21 18:37:15 +00:00
Benjamin Kramer 5cff13a3fb Remove unused variables.
llvm-svn: 148635
2012-01-21 10:42:44 +00:00
Craig Topper 39bc1e4d25 Fix PR11819 introduced by r148537. I'd commit the test case, but the generated code is terrible as it gets fully scalarized. Expect a future commit to fix that.
llvm-svn: 148632
2012-01-21 08:49:33 +00:00
Jim Grosbach 78dcaed8ca Thumb2 'add rd, pc, imm' alternate form for 'adr' instruction.
llvm-svn: 148601
2012-01-21 00:07:56 +00:00
Devang Patel ce6a2ca8c8 Intel syntax: Robustify register parsing.
llvm-svn: 148591
2012-01-20 22:32:05 +00:00
David Blaikie 46a9f016c5 More dead code removal (using -Wunreachable-code)
llvm-svn: 148578
2012-01-20 21:51:11 +00:00
Devang Patel d0930fff85 Intel syntax: Parse ... PTR [-8]
llvm-svn: 148570
2012-01-20 21:21:01 +00:00
Devang Patel f36613cb45 Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax.
llvm-svn: 148569
2012-01-20 21:14:06 +00:00
Bob Wilson 6c7aaec077 ARM vector any_extends need to be selected to vmovl. <rdar://problem/10723651>
We have patterns for vector sext and zext operations but were missing
anyext.  Without those patterns, codegen will fail when the selection DAG
has any_extend nodes.

llvm-svn: 148568
2012-01-20 20:59:56 +00:00
Jim Grosbach 90f5780fc1 VST2 four-register w/ update pseudos for fixed/register update.
rdar://10724489

llvm-svn: 148560
2012-01-20 19:16:00 +00:00
Jim Grosbach a9d36fbca7 NEON use vmov.i32 to splat some f32 values into vectors.
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.

rdar://10616677

llvm-svn: 148556
2012-01-20 18:09:51 +00:00
Benjamin Kramer 084b9f4134 Remove a bunch of unused variable assignments.
Found by the clang static analyzer.

llvm-svn: 148541
2012-01-20 14:42:32 +00:00
Craig Topper a409479023 Improve 256-bit shuffle splitting to allow 2 sources in each 128-bit lane. As long as only a single lane of the source is used in the lane in the destination. This makes the splitting match much closer to what happens with 256-bit shuffles when AVX is disabled and only 128-bit XMM is allowed.
llvm-svn: 148537
2012-01-20 09:29:03 +00:00
Craig Topper 3469212c82 Add support for selecting 256-bit PALIGNR.
llvm-svn: 148532
2012-01-20 05:53:00 +00:00
Eli Friedman 32c7c25dcb Support MSVC x86-32 sret convention. PR11688. Patch by Joe Groff.
llvm-svn: 148513
2012-01-20 00:05:46 +00:00
Benjamin Kramer 116e99a469 Silence warnings about mixing enums.
llvm-svn: 148495
2012-01-19 21:11:13 +00:00
Devang Patel f83dcfd052 Post process 'and', 'sub' instructions and select better encoding, if available.
llvm-svn: 148489
2012-01-19 18:40:55 +00:00
Devang Patel 2529dd9e00 Intel syntax: There is no need to create unary expr for simple negative displacement.
llvm-svn: 148486
2012-01-19 18:15:51 +00:00
Devang Patel 4a62ff9bcb Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available.
llvm-svn: 148485
2012-01-19 17:53:25 +00:00
Evgeniy Stepanov 4c7eb477b5 Emit ARM EHABI unwinding instructions for 3 more Thumb instructions.
llvm-svn: 148473
2012-01-19 12:53:06 +00:00
Craig Topper a875b7ccc7 Folding table additions and fixes for AVX.
llvm-svn: 148467
2012-01-19 08:50:38 +00:00
Craig Topper 80576e8d1f Merge 128-bit and 256-bit SHUFPS/SHUFPD handling.
llvm-svn: 148466
2012-01-19 08:19:12 +00:00
Jim Grosbach 235c8d2d94 ARM assembly diagnostic caret in better position for FPImm.
llvm-svn: 148459
2012-01-19 02:47:30 +00:00
Jim Grosbach 44e5c39c29 Thumb2 relaxation for tADR to t2ADR.
llvm-svn: 148456
2012-01-19 02:09:38 +00:00
Jim Grosbach b008df40d3 Add comment and fix range check in condition.
llvm-svn: 148455
2012-01-19 01:50:30 +00:00
Evan Cheng 2879467d4e - Slight change to finalizeBundle() interface. LastMI is not exclusive (pointing
to instruction right after the last instruction in the bundle.
- Add a finalizeBundle() variant that doesn't specify LastMI. Instead, the code
  will find the last instruction in the bundle by following the 'InsideBundle'
  marker. This is useful in case bundles are formed early (i.e. during MI
  scheduling) but finalized later (i.e. after register allocator has finished
  rewriting virtual registers with physical registers).

llvm-svn: 148444
2012-01-19 00:46:06 +00:00
Nick Lewycky ecc0084f72 Add a TargetOption for disabling tail calls.
llvm-svn: 148442
2012-01-19 00:34:10 +00:00
Evan Cheng 1eb2bb2295 Rename Finalizebundle to finalizeBundle to conform to coding guideline.
llvm-svn: 148440
2012-01-19 00:06:10 +00:00
Jakob Stoklund Olesen ff482f733b Add experimental -x86-use-regmask command line option.
It adds register mask operands to x86 call instructions.  Once all the
backend passes support register mask operands, this will be permanently
enabled.

llvm-svn: 148438
2012-01-18 23:52:22 +00:00
Jakob Stoklund Olesen f1fb1d2375 Ignore register mask operands when lowering instructions to MC.
This is similar to implicit register operands.  MC doesn't understand
register liveness and call clobbers.

llvm-svn: 148437
2012-01-18 23:52:19 +00:00
Jim Grosbach 94298a906a Thumb2 alternate syntax for LDR(literal) and friends.
Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".

rdar://10250964

llvm-svn: 148432
2012-01-18 22:46:46 +00:00
Devang Patel de47cced25 Process instructions after match to select alternative encoding which may be more desirable.
llvm-svn: 148431
2012-01-18 22:42:29 +00:00
Jim Grosbach cbd3f27354 Replace FIXME with explanatory comment.
llvm-svn: 148427
2012-01-18 22:04:42 +00:00
Jim Grosbach cb80eb2e75 Thumb2 relaxation for LDR(literal).
If the fixup is out of range for the Thumb1 instruction, relax it
to the Thumb2 encoding instead.

rdar://10711829

llvm-svn: 148424
2012-01-18 21:54:16 +00:00
Jim Grosbach 9ab3d8be4e Rename pattern for clarity.
llvm-svn: 148422
2012-01-18 21:54:09 +00:00
Jim Grosbach e2d298168c Tidy up. 80 columns.
llvm-svn: 148401
2012-01-18 18:52:20 +00:00
Jim Grosbach aba3de99c0 Tidy up. MCAsmBackend naming conventions.
llvm-svn: 148400
2012-01-18 18:52:16 +00:00
Jim Grosbach adcc938c46 Thumb2 load/store fixups don't set the thumb bit.
Load/store instructions w/ a fixup to be relative a function marked as thumb
don't use the low bit to specify thumb vs. non-thumb like interworking
branches do, so don't set it when dealing with those fixups.

rdar://10348687.

llvm-svn: 148366
2012-01-18 00:40:25 +00:00
Jim Grosbach 3b50c9ec7f Move some ARM specific MCAssmebler bits into the ARMAsmBackend.
llvm-svn: 148364
2012-01-18 00:23:57 +00:00
Jakob Stoklund Olesen f43b599550 Add a CoveredBySubRegs property to Register descriptions.
When set, this bit indicates that a register is completely defined by
the value of its sub-registers.

Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers.  For example, the
ARM registers D8-D15 are callee-saved.  This now automatically implies
that Q4-Q7 are call-preserved.

Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.

llvm-svn: 148363
2012-01-18 00:16:39 +00:00
Jakob Stoklund Olesen fdbb12b235 Implement ARMBaseRegisterInfo::getCallPreservedMask().
Move ARM callee-saved lists into ARMCallingConv.td.

llvm-svn: 148357
2012-01-17 23:09:00 +00:00
Jakob Stoklund Olesen d51a710bde Move X86 callee saved register lists to the X86CallConv .td file.
Add a trivial implementation of the getCallPreservedMask() hook.

llvm-svn: 148347
2012-01-17 22:47:01 +00:00
Devang Patel c9ed518792 Intel syntax: Fix parser match class to check memory operand size.
llvm-svn: 148338
2012-01-17 21:48:03 +00:00
Devang Patel a7143b6a2b Intel syntax: Parse "BYTE PTR [RDX + RCX]"
llvm-svn: 148334
2012-01-17 21:25:10 +00:00
Devang Patel 2ed6718616 Untabify.
llvm-svn: 148322
2012-01-17 19:09:22 +00:00
Devang Patel 8b39be79ad Intel syntax: Do not unncessarily create plus expression for memory operand displacement.
llvm-svn: 148321
2012-01-17 19:08:07 +00:00
Devang Patel 41b9ddeb7a Intel syntax: Robustify memory operand parsing.
llvm-svn: 148312
2012-01-17 18:00:18 +00:00
Nadav Rotem 86c3807b99 Fix warning.
llvm-svn: 148301
2012-01-17 09:31:09 +00:00
Nadav Rotem 86e5390dbf Fix 11769.
In CanXFormVExtractWithShuffleIntoLoad we assumed that EXTRACT_VECTOR_ELT can be later handled by the DAGCombiner.
However, in some cases on AVX, the EXTRACT_VECTOR_ELT is legalized to EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which
currently is not handled by the DAGCombiner. In this patch I added a check that we only extract from the XMM part.

llvm-svn: 148298
2012-01-17 09:13:19 +00:00
Craig Topper 9cafcd8baa Remove unnecessary AVX check from an assert. hasSSE2 is enough.
llvm-svn: 148295
2012-01-17 08:23:44 +00:00
Andrew Trick 8093eac51d Moving options declarations around.
More short term hackery until we have a way to configure passes that work on LiveIntervals.

llvm-svn: 148289
2012-01-17 06:54:59 +00:00
Craig Topper 37b10ef250 Fix a crasher when PerformShiftCombine receives a BUILD_VECTOR of all UNDEF. Probably could use better handling in DAG combine or getNode. Fixes PR11772.
llvm-svn: 148285
2012-01-17 04:44:50 +00:00
David Blaikie 486df738c3 Removing unused default switch cases in switches over enums that already account for all enumeration values explicitly.
(This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them)

llvm-svn: 148262
2012-01-16 23:24:27 +00:00
Hal Finkel b1691ccaaa Cleanup PPC RLWINM8 vs RLWINM
No test case: output assembly will be identical.

llvm-svn: 148261
2012-01-16 23:22:50 +00:00
Eli Friedman 206ca569aa Make sure the non-SSE lowering for fences correctly clobbers EFLAGS. PR11768.
llvm-svn: 148240
2012-01-16 16:42:21 +00:00
Eli Friedman 75e3db4c7a Get rid of unused codegen-only instruction.
llvm-svn: 148239
2012-01-16 16:29:35 +00:00
Craig Topper db8890aedd Give priority to AVX over SSE for 128-bit floating point unpck instructions.
llvm-svn: 148233
2012-01-16 09:56:42 +00:00
David Blaikie 5d8e42755c Refactor variables unused under non-assert builds (& remove two entirely unused variables).
llvm-svn: 148230
2012-01-16 05:17:39 +00:00
Nadav Rotem 57935243bd [AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits.
We know that the blend instructions only use the MSB, so if the mask is
sign-extended then we can convert it into a SHL instruction. This is a
common pattern because the type-legalizer sign-extends the i1 type which
is used by the LLVM-IR for the condition.

Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL.

llvm-svn: 148225
2012-01-15 19:27:55 +00:00
Benjamin Kramer 339ced4e34 Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through CodeGen.
llvm-svn: 148218
2012-01-15 13:16:05 +00:00
Craig Topper c10e1abaf3 Fix the memop type on a couple 256-bit AVX instructions that were using f128mem instead of f256mem.
llvm-svn: 148196
2012-01-14 18:29:57 +00:00
Craig Topper d78429f850 Add a bunch of AVX instructions to the folding tables. Also fixed the alignment on 256-bit AVX2 instructions.
llvm-svn: 148194
2012-01-14 18:14:53 +00:00
Evan Cheng 6bb95253eb After r147827 and r147902, it's now possible for unallocatable registers to be
live across BBs before register allocation. This miscompiled 197.parser
when a cmp + b are optimized to a cbnz instruction even though the CPSR def
is live-in a successor.
        cbnz    r6, LBB89_12
...
LBB89_12:
        ble     LBB89_1

The fix consists of two parts. 1) Teach LiveVariables that some unallocatable
registers might be liveouts so don't mark their last use as kill if they are.
2) ARM constantpool island pass shouldn't form cbz / cbnz if the conditional
branch does not kill CPSR.

rdar://10676853

llvm-svn: 148168
2012-01-14 01:53:46 +00:00
Chad Rosier 71a185c5c6 Fix pasto from r146196.
llvm-svn: 148167
2012-01-14 01:50:21 +00:00
Jakob Stoklund Olesen 35545421c8 Use RegisterTuples to generate pseudo-registers.
The QQ and QQQQ registers are not 'real', they are pseudo-registers used
to model some vld and vst instructions.

This makes the call clobber lists longer, but I intend to get rid of
those soon.

llvm-svn: 148151
2012-01-13 22:55:42 +00:00
Devang Patel 7066d28043 Revert r148131, it was committed before it was ready.
llvm-svn: 148134
2012-01-13 19:28:58 +00:00
Devang Patel 7ecdc6d4f5 Refactor.
llvm-svn: 148131
2012-01-13 19:12:18 +00:00
Craig Topper e52d86a740 Convert SHUFPD with the same register for both sources to PSHUFD if it would prevent a register copy. Similar to SHUFPS, but requires the mask to be converted.
llvm-svn: 148112
2012-01-13 09:21:41 +00:00
Craig Topper b1c2ebf6ee use v8i32 as optimal mem type over v8f32 if AVX2 is enabled. Similar to SSE2 vs SSE1.
llvm-svn: 148109
2012-01-13 08:32:21 +00:00
Craig Topper cb7e13d7c0 Make X86 instruction selection use 256-bit VPXOR for build_vector of all ones if AVX2 is enabled. This gives the ExeDepsFix pass a chance to choose FP vs int as appropriate. Also use v8i32 as the type for getZeroVector if AVX2 is enabled. This is consistent with SSE2 using prefering v4i32.
llvm-svn: 148108
2012-01-13 08:12:35 +00:00
Craig Topper 9f14d9f939 Add patterns for v16i16 and v32i8 immAllZerosV to select VPXOR to match v4i64 and v8i32.
llvm-svn: 148106
2012-01-13 06:59:47 +00:00
Andrew Trick e77e84e4b7 Added the MachineSchedulerPass skeleton.
llvm-svn: 148105
2012-01-13 06:30:30 +00:00
Craig Topper a4c5a47b97 Use 8i32 constant pool entry for converting AVX2_SETALLONES. Possibly fixes PR11750.
llvm-svn: 148101
2012-01-13 06:12:41 +00:00
Craig Topper 2aa07f832e Fix typo in PerformAddCombine that caused any vector type to be checked for horizontal add/sub if AVX2 is enabled. This caused an assert to fail for non 128/256-bit vectors when done before type legalizing. Fixes PR11749.
llvm-svn: 148096
2012-01-13 05:04:25 +00:00
Bill Wendling 9c8456f7ef Fix off-by-one error.
llvm-svn: 148077
2012-01-13 00:41:53 +00:00
Bill Wendling ee5eaebc58 Fix the code that was WRONG.
The registers are placed into the saved registers list in the reverse order,
which is why the original loop was written to loop backwards.

llvm-svn: 148064
2012-01-12 23:05:03 +00:00
Elena Demikhovsky 060f6ccdb8 Fixed a bug in LowerVECTOR_SHUFFLE caused assertion failure
lc: X86ISelLowering.cpp:6480: llvm::SDValue llvm::X86TargetLowering::LowerVECTOR_SHUFFLE(llvm::SDValue, llvm::SelectionDAG&) const: Assertion `V1.getOpcode() != ISD::UNDEF&&  "Op 1 of shuffle should not be undef"' failed.
Added a test.

llvm-svn: 148044
2012-01-12 20:33:10 +00:00
Rafael Espindola 00e861ed57 Support segmented stacks on 64-bit FreeBSD.
This patch uses tcb_spare field in the tcb structure to store info.
Patch by Jyun-Yan You.

llvm-svn: 148041
2012-01-12 20:24:30 +00:00
Rafael Espindola 10745d3381 Support segmented stacks on win32.
Uses the pvArbitrary slot of the TIB, which is reserved for applications. We
only support frames with a static size.

llvm-svn: 148040
2012-01-12 20:22:08 +00:00
Devang Patel 4a6e778aae Rename X86ATTAsmParser -> X86AsmParser
We are using one parser to parse att as well as intel style syntax.

llvm-svn: 148032
2012-01-12 18:03:40 +00:00
Benjamin Kramer 9ece950ddb After Jakob's r147938 exception handling on i386 was completely broken.
Restore the (obviously wrong) behavior from before r147938 without relying on
undefined behavior. Add a fat FIXME note.

This should fix nightly tester failures.

llvm-svn: 148030
2012-01-12 17:37:18 +00:00
Nadav Rotem 0a0a829bea Fix a bug in the AVX 256-bit shuffle code in cases where the splat element is on the boundary of two 128-bit vectors.
The attached testcase was stuck in an endless loop.

llvm-svn: 148027
2012-01-12 15:31:55 +00:00
Benjamin Kramer 5b3aa60b44 X86: Generalize the x << (y & const) optimization to also catch masks with more set bits set than 31 or 63.
llvm-svn: 148024
2012-01-12 12:41:34 +00:00
Devang Patel fc6be102ae Add predicate method check match memory operand size, if available.
In att style asm syntax memory operand size is derived from suffix attached with mnemonic.  In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction.

llvm-svn: 148006
2012-01-12 01:51:42 +00:00
Devang Patel 46831de240 Add intel style operand parser skeleton.
This is a work in progress.

llvm-svn: 148002
2012-01-12 01:36:43 +00:00
Chandler Carruth eb21da060b Switch all of the uses of my InsertDAGNode helper to follow the exact
same pattern. We already had this pattern is a few places, but others
tried to make a rough approximation of an actual DAG structure. As not
everywhere went to this trouble, nothing could rely on this being done.
In fact, I've checked all references to these node Ids, and the ones
that are using the topo-sort properties are actually satisfied with
a strict-weak-ordering. The requirement appears to be that Use >= Def.

I've added a big blurb of comments to this bit of the transform to
clarify why the order is so important for the next reader of the code.

I'm starting with this change as it is very small, and trivially
reverted if something breaks or the >= above really does need to be >.
If that proves the case, we can hide the problem by reverting this
patch, but the problem exists elsewhere as well, and so a more
comprehensive solution will be needed.

llvm-svn: 148001
2012-01-12 01:34:44 +00:00
Eric Christopher d284c1d80d Fix assert.
llvm-svn: 147966
2012-01-11 20:55:27 +00:00