Commit Graph

192576 Commits

Author SHA1 Message Date
Craig Topper 870363a22d [X86] Explicitly pass Destination VT and debug location to BuildFILD. NFC
We'd already passed most everything else. Might was well pass
these two things and stop passing Op.
2020-02-26 16:26:46 -08:00
Craig Topper 15e2831fcd [X86] Explicitly pass Pointer, MachinePointerInfo and Alignment to BuildFILD.
Previously this code was called into two ways, either a FrameIndexSDNode
was passed in StackSlot. Or a load node was passed in the argument
called StackSlot. This was determined by a dyn_cast to FrameIndexSDNode.

In the case of a load, we had to go find the real pointer from
operand 0 and cast the node to MemSDNode to find the pointer info.

For the stack slot case, the code assumed that the stack slot
was perfectly aligned despite not being the creator of the slot.

This commit modifies the interface to make the caller responsible
for passing all of the required information to avoid all the
guess work and reverse engineering.

I'm not aware of any issues with the original code after an
earlier commit to fix the alignment of one of the stack objects.
This is just clean up to make the code less surprising.
2020-02-26 16:26:26 -08:00
Erik Pilkington 30f4362040 Disable memory leak checking in a test to work around a bot failure
This leak is expected, see the discussion on commit 85fb997
2020-02-26 14:51:50 -08:00
Adrian Prantl a5a07b8041 Visit previously unreachable nodes in the debug info metadata verifier.
This allows for diagnosing malformed LLVM IR debug info metadata such
as the one in the testcase.

<rdar://problem/59756060>

Differential Revision: https://reviews.llvm.org/D75212
2020-02-26 14:48:08 -08:00
Craig Topper 77d9b7b2cd [X86] Query constant pool object alignment instead of hardcoding. 2020-02-26 14:45:39 -08:00
Craig Topper 9c1a707ba3 [X86] Use proper alignment for stack temporary and correct MachinePointerInfo for stack accesses in LowerUINT_TO_FP. 2020-02-26 14:45:38 -08:00
Craig Topper a8186935ae [X86] Use correct MachineMemOperand for stack load in LowerFLT_ROUNDS_ 2020-02-26 14:45:38 -08:00
Craig Topper 14306ce80c [X86] Add proper MachinePointerInfo to the loads/stores created for moving data between SSE and X87 in X86DAGToDAGISel::PreprocessISelDAG 2020-02-26 14:45:37 -08:00
Amara Emerson 65f99b5383 [AArch64][GlobalISel] Fixup <32b heterogeneous regbanks of G_PHIs just before selection.
Since all types <32b on gpr end up being assigned gpr32 regclasses, we can end
up with PHIs here which try to select between a gpr32 and an fpr16. Ideally RBS
shouldn't be selecting heterogenous regbanks for operands if possible, but we
still need to be able to deal with it here.

To fix this, if we have a gpr-bank operand < 32b in size and at least one other
operand is on the fpr bank, then we add cross-bank copies to homogenize the
operand banks. For simplicity the bank that we choose to settle on is whatever
bank the def operand has. For example:

%endbb:
  %dst:gpr(s16) = G_PHI %in1:gpr(s16), %bb1, %in2:fpr(s16), %bb2
 =>
%bb2:
  ...
  %in2_copy:gpr(s16) = COPY %in2:fpr(s16)
  ...
%endbb:
  %dst:gpr(s16) = G_PHI %in1:gpr(s16), %bb1, %in2_copy:gpr(s16), %bb2

Differential Revision: https://reviews.llvm.org/D75086
2020-02-26 14:10:32 -08:00
Alexey Lapshin 949134e2fe [DebugInfo][NFC] Remove handler with ErrorPolicy from DWARFContext.
Summary:
Current LLVM code base does not use error handler with ErrorPolicy.
This patch removes ErrorPolicy from DWARFContext.

This patch is extracted from the D74308.

Reviewers: jhenderson, dblaikie, grimar, aprantl, JDevlieghere

Reviewed By: grimar

Subscribers: hiraditya, llvm-commits

Tags: #llvm, #debug-info

Differential Revision: https://reviews.llvm.org/D75118
2020-02-27 00:42:37 +03:00
Philip Reames eca4bfea3d [MC] Pull out a relaxFragment helper [NFC]
Having this as it's own function helps to reduce indentation and allows use of return instead of wiring a value over the switch.  A lambda would have also worked, but with slightly deeper nesting.
2020-02-26 13:37:12 -08:00
Alexander Shaposhnikov f79b81fbe2 [llvm-objcopy] Enable --discard-all for MachO
In this diff we enable the option --discard-all for MachO.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D75104
2020-02-26 12:51:15 -08:00
Adrian Prantl 22cb36c86b [dsymutil] Avoid copying swiftinterfaces from the SDK into the dsym bundle
This patch fixes a bug that would cause dsymutil to collect
.swiftinterface files for the Swift stdlib and other SDK
modules. There is no advantage in copying these since they should be
loaded from the ones bundled with LLDB's embedded Swift compiler
instead and copying them will cause LLDB to recompile them from source
instead of loading their prebuilt cached counterparts in the SDK.

rdar://problem/57463247

Differential Revisions: https://reviews.llvm.org/D75196
2020-02-26 12:22:50 -08:00
Eric Astor 85b641c27a [ms] Rename ParsingInlineAsm functions/variables to reflect MS-specificity.
Summary: ParsingInlineAsm was a misleading name. These values are only set for MS-style inline assembly.

Reviewed By: rnk

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D75198
2020-02-26 15:19:40 -05:00
Sanjay Patel 25c6544f32 [VectorCombine] add a debug flag to skip all transforms
As suggested in D75145 -

I'm not sure why, but several passes have this kind of disable/enable flag
implemented at the pass manager level. But that means we have to duplicate
the flag for both pass managers and add code to check the flag every time
the pass appears in the pipeline.

We want a debug option to see if this pass is misbehaving regardless of the
pass managers, so just add a disablement check at the single point before
any transforms run.

Differential Revision: https://reviews.llvm.org/D75204
2020-02-26 15:15:42 -05:00
Nikita Popov 00f54050f7 [SimpleLoopUnswitch] Remove unnecessary include; NFC 2020-02-26 20:40:43 +01:00
Nikita Popov 9d9633fb70 [CVP] Simplify cmp of local phi node
CVP currently does not simplify cmps with instructions in the same
block, because LVI getPredicateAt() currently does not provide
much useful information for that case (D69686 would change that,
but is stuck.) However, if the instruction is a Phi node, then
LVI can compute the result of the predicate by threading it into
the predecessor blocks, which allows it simplify some conditions
that nothing else can handle. Relevant code:
6d6a4590c5/llvm/lib/Analysis/LazyValueInfo.cpp (L1904-L1927)

Differential Revision: https://reviews.llvm.org/D72169
2020-02-26 20:36:41 +01:00
Nikita Popov 7da3b5e45c [InstCombine] Simplify DCE code; NFC
As pointed out on D75008, MadeIRChange is already set by
eraseInstFromFunction(), which also already does a debug print.
2020-02-26 20:33:00 +01:00
Nikita Popov 3e440545dc [CVP] Add test for cmp of local phi; NFC 2020-02-26 20:32:59 +01:00
Ayke van Laethem 6afc3de42f
[AVR] Fix private label prefix
This is a small pet peeve from me. This change makes sure the AVR backend uses
the correct private label prefix (.L) so that private labels are hidden in
avr-objdump.

Example code:

    define i8 @foo(i1 %cond) {
      br i1 %cond, label %then, label %else
    then:
      ret i8 3
    else:
      ret i8 5
    }

When compiling this:
  llc -march=avr -filetype=obj -o test.o test.ll
and then dumping it:
  avr-objdump -d test.o
You would previously get an ugly temporary label:

    00000000 <foo>:
       0:        81 70       andi       r24, 0x01    ; 1
       2:        80 30       cpi        r24, 0x00    ; 0
       4:        f9 f3       breq       .-2          ; 0x4 <foo+0x4>
       6:        83 e0       ldi        r24, 0x03    ; 3
       8:        08 95       ret

    0000000a <LBB0_2>:
       a:        85 e0       ldi        r24, 0x05    ; 5
       c:        08 95       ret

This patch fixes that, the output is now:

    00000000 <foo>:
       0:        81 70       andi       r24, 0x01    ; 1
       2:        80 30       cpi        r24, 0x00    ; 0
       4:        01 f0       breq       .+0          ; 0x6 <foo+0x6>
       6:        83 e0       ldi        r24, 0x03    ; 3
       8:        08 95       ret
       a:        85 e0       ldi        r24, 0x05    ; 5
       c:        08 95       ret

Note that as you can see the breq operand is different. However it is
still the same after linking:

       4:        11 f0       breq       .+4

Differential Revision: https://reviews.llvm.org/D75124
2020-02-26 20:32:25 +01:00
Ayke van Laethem 165f707f9d
[AVR] Don't adjust addresses by 2 for absolute values
Adjusting by 2 breaks DWARF output. With this fix, programs start to
compile and produce valid DWARF output.

Differential Revision: https://reviews.llvm.org/D74213
2020-02-26 20:32:24 +01:00
Nikita Popov 56f7de5baa [InstCombine] Remove trivially empty ranges from end
InstCombine removes pairs of start+end intrinsics that don't
have anything in between them. Currently this is done by starting
at the start intrinsic and scanning forwards. This patch changes
it to start at the end intrinsic and scan backwards.

The motivation here is as follows: When we process the start
intrinsic, we have not yet looked at the following instructions,
which may still get folded/removed. If they do, we will only be
able to remove the start/end pair on the next iteration. When we
process the end intrinsic, all the instructions before it have
already been visited, and we don't run into this problem.

Differential Revision: https://reviews.llvm.org/D75011
2020-02-26 20:04:11 +01:00
Reid Kleckner 30dae38349 Fix LLP64 detection in SwapByteOrder.h
MSVC does not define __LONG_MAX__, so we were just getting lucky in this
conditional:
  #if __LONG_MAX__ == __INT_MAX__

Undefined identifiers evaluate to zero in preprocessor conditionals, so
this became true, which happens to work for MSVC platforms.

Instead, use this pattern and let the compiler constant fold:
  return sizeof(long) == sizeof(int) ? SwapByteOrder_32((uint32_t)C)
                                     : SwapByteOrder_64((uint64_t)C);
2020-02-26 10:59:45 -08:00
Krzysztof Parzyszek 7691790dfd [Hexagon] Improve casting of boolean HVX vectors to scalars
- Mark memory access for bool vectors as disallowed in target lowering.
  This will prevent combining bitcasts of bool vectors with stores.
- Replace the actual bitcasting code with a faster version.
- Handle casting of v16i1 to i16.
2020-02-26 12:46:52 -06:00
Reid Kleckner 34312ed24e Remove unneeded Compiler.h and DataTypes.h includes, NFC 2020-02-26 10:36:17 -08:00
Greg Clayton e4af56db27 Fix buildbots after recent GSYM commit.
Added llvm-gsymutil to LLVM_TEST_DEPENDS.
2020-02-26 10:30:04 -08:00
Krzysztof Parzyszek fd7c2e24c1 [SDAG] Add SDNode::values() = make_range(values_begin(), values_end())
Also use it in a few places to simplify code a little bit.  NFC
2020-02-26 12:07:38 -06:00
Juneyoung Lee 4f71252cf8 [TTI] Let getOperationCost assume that Freeze is free 2020-02-27 02:56:11 +09:00
Hiroshi Yamauchi 59fb9cde7a Devirtualize a call on alloca without waiting for post inline cleanup and next
DevirtSCCRepeatedPass iteration.  Needs ReviewPublic

This aims to fix a missed inlining case.

If there's a virtual call in the callee on an alloca (stack allocated object) in
the caller, and the callee is inlined into the caller, the post-inline cleanup
would devirtualize the virtual call, but if the next iteration of
DevirtSCCRepeatedPass doesn't happen (under the new pass manager), which is
based on a heuristic to determine whether to reiterate, we may miss inlining the
devirtualized call.

This enables inlining in clang/test/CodeGenCXX/member-function-pointer-calls.cpp.
2020-02-26 09:51:24 -08:00
Sean Fertile 73c3b52676 [PowerPC][NFC] Convert grep usage to FileCheck in lit test. 2020-02-26 12:28:18 -05:00
Reid Kleckner 465dca79b3 Avoid SmallString.h include in MD5.h, NFC
Saves 200 includes, which is mostly immaterial.
2020-02-26 09:10:24 -08:00
Fangrui Song 6503aadcc6 [llvm-objcopy][test] Improve empty section tests
empty-sections.test: add two tests adapted from @jhenderson's https://reviews.llvm.org/D74755#1882221
strip-non-alloc.test: improve. D74755 will change the attribution of an empty section.

They mostly test the behavior of Object.cpp:sectionWithinSegment : how we attribute sections to segments.
`ParentSegment` can affect some subtle layout decisions.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D74879
2020-02-26 08:57:23 -08:00
Sanjay Patel b3d0c79836 [DAGCombiner] avoid narrowing fake fneg vector op
This may inhibit vector narrowing in general, but there's
already an inconsistency in the way that we deal with this
pattern as shown by the test diff.

We may want to add a dedicated function for narrowing fneg.
It's often folded into some other op, so moving it away from
other math ops may cause regressions that we would not see
for normal binops.

See D73978 for more details.
2020-02-26 11:25:56 -05:00
LLVM GN Syncbot 299c3e13fb [gn build] Port 3c36d8dad5 2020-02-26 16:09:48 +00:00
Pavel Labath 3c36d8dad5 Introduce DWARFDataExtractor::getInitialLength
Summary:
This patch introduces a function to house the code needed to do the
DWARF64 detection dance. The function decodes the initial length field
and returns it as a pair containing the actual length, and the DWARF
encoding.

This patch does _not_ attempt to handle the problem of detecting lengths
which extend past the size of the section, or cases when reads of a
single contribution accidentally escape beyond its specified length, but
I think it's useful in its own right.

Reviewers: dblaikie, jhenderson, ikudrin

Subscribers: hiraditya, probinson, aprantl, JDevlieghere, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74560
2020-02-26 17:07:58 +01:00
Sanjay Patel 894ce940db [AArch64] add tests for fake fneg; NFC
See comments in D73978 for background.
2020-02-26 10:56:26 -05:00
Simon Pilgrim bbb0933e3d [DAG] visitRotate - modulo non-uniform constant rotation amounts 2020-02-26 15:43:12 +00:00
Pavel Labath ced45978a2 Recommit "[DWARFDebugLine] Avoid dumping prologue members we did not parse"
The patch was reverted in 69da40033 because of test failures on windows.
The problem was the unpredictable order of some of the error messages,
which I've tried to strenghten in that patch.

It turns out this is not possible to do in verbose mode because there
the data is being writted as it is being parsed. No amount of flushing
(as I've done in the non-verbose mode) will help that. Indeed, even
without any buffering the warning messages can end in the middle of a
line in non-verbose mode.

In this patch, I have reverted the changes which tested the relative
position of the warning message, except for the messages about
unsupported initial length, which are the ones I really wanted to test,
and which do come out reasonably.

The original commit message was:

This patch if motivated by D74560, specifically the subthread about what
to print upon encountering reserved initial length values.

If the debug_line prologue has an unsupported version, we skip parsing
the rest of the data. If we encounter an reserved initial length field,
we don't even parse the version. However, we still print out all members
(with value 0) in the dump function.

This patch introduces early exits in the Prologue::dump function so that
we print only the fields that were parsed successfully. In case of an
unsupported version, we skip printing all subsequent prologue fields --
because we don't even know if this version has those fields. In case of a
reserved unit length, we don't print anything -- if the very first field
of the prologue is invalid, it's hard to say if we even have a prologue
to begin with.

Note that the user will still be able to see the invalid/reserved
initial length value in the error message. I've modified (reordered)
debug_line_invalid.test to show that the error message comes straight
after the debug_line offset. I've also added some flush() calls to the
dumping code to ensure this is the case in all situations (without that,
the warnings could get out of sync if the output was not a terminal -- I
guess this is why std::iostreams have the tie() function).

Reviewers: jhenderson, ikudrin, dblaikie

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D75043
2020-02-26 16:42:25 +01:00
Nicolai Hähnle d6b05fccb7 Full fix for "AMDGPU/SIInsertSkips: Fix the determination of whether early-exit-after-kill is possible" (hopefully)
Properly preserve the MachineDominatorTree in all cases.

Change-Id: I54cf0c0a20934168a356920ba8ed5097a93c4131
2020-02-26 16:21:44 +01:00
Simon Tatham 9eb3cc10b2 [ARM,MVE] Add predicated intrinsics for many unary functions.
Summary:
This commit adds the predicated MVE intrinsics for the same set of
unary operations that I added in their unpredicated forms in

* D74333 (vrint)
* D74334 (vrev)
* D74335 (vclz, vcls)
* D74336 (vmovl)
* D74337 (vmovn)

but since the predicated versions are a lot more similar to each
other, I've kept them all together in a single big patch. Everything
here is done in the standard way we've been doing other predicated
operations: an IR intrinsic called `@llvm.arm.mve.foo.predicated` and
some isel rules that match that alongside whatever they accept for the
unpredicated version of the same instruction.

In order to write the isel rules conveniently, I've refactored the
existing isel rules for the affected instructions into multiclasses
parametrised by a vector-type class, in the usual way. All those
refactorings are intended to leave the existing isel rules unchanged:
the only difference should be that new ones for the predicated
intrinsics are introduced.

The only tiny infrastructure change I needed in this commit was to
change the implementation of `IntrinsicMX` in `arm_mve_defs.td` so
that the records it defines are anonymous rather than named (and use
`NameOverride` to set the output intrinsic name), which allows me to
call it twice in two multiclasses with the same `NAME` without a
tablegen-time error.

Reviewers: dmgreen, MarkMurrayARM, miyuki, ostannard

Reviewed By: MarkMurrayARM

Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D75165
2020-02-26 15:12:07 +00:00
Xiangling Liao e7375e9932 [AIX] Remove whitelist checking for ExternalSymbolSDNodes
Allow all ExternalSymbolSDNode on AIX, and rely on the linker error to find
symbols which we don't have definitions from any library/compiler-rt.

Differential Revision: https://reviews.llvm.org/D75075
2020-02-26 10:09:25 -05:00
Nicolai Hähnle 0aec4b418e Quick fix for bot failure on "AMDGPU/SIInsertSkips: Fix the determination of whether early-exit-after-kill is possible"
Apparently the dominator tree update is incorrect, will investigate.

Change-Id: Ie76f8d11b22a552af1f098c893773f3d85e02d4f
2020-02-26 16:02:22 +01:00
Jay Foad 09a6b26753 AMDGPU: Fix some more incorrect check lines 2020-02-26 14:37:22 +00:00
Nicolai Hähnle 0f1df48925 AMDGPU/SIInsertSkips: Fix the determination of whether early-exit-after-kill is possible
Summary:
The old code made some incorrect assumptions about the order in which
basic blocks are laid out in a function. This could lead to incorrect
early-exits, especially when kills occurred inside of loops.

The new approach is to check whether the point where the conditional
kill occurs dominates all reachable code. If that is the case, there
cannot be any other threads in the wave that are waiting to rejoin
at a later point in the CFG, i.e. if exec=0 at that point, then all
threads really are dead and we can exit the wave.

Make some other minor cleanups to the pass while we're at it.

v2: preserve the dominator tree

Reviewers: arsenm, cdevadas, foad, critson

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74908

Change-Id: Ia0d2b113ac944ad642d1c622b6da1b20aa1aabcc
2020-02-26 15:30:42 +01:00
Nico Weber cfbe889af5 [gn build] re-"gn format" all gn files 2020-02-26 08:38:34 -05:00
evgeny 8f8756d465 [Assembler] Allow assembling empty index with non-zero flags
Differential revision: https://reviews.llvm.org/D74778
2020-02-26 16:34:11 +03:00
Nico Weber ce75c3d2b6 [gn build] (manually) port 2f6cc21f44 2020-02-26 08:36:05 -05:00
Nico Weber 1b30b49436 [gn build] (manually) merge e058667a2e 2020-02-26 07:33:32 -05:00
Hans Wennborg 546918cbb4 Revert "[compiler-rt] Add a critical section when flushing gcov counters"
See discussion on PR44792.

This reverts commit 02ce9d8ef5.

It also reverts the follow-up commits
8f46269f0 "[profile] Don't dump counters when forking and don't reset when calling exec** functions"
62c7d8402 "[profile] gcov_mutex must be static"
2020-02-26 13:27:44 +01:00
Kerry McLaughlin 9c859fc54d [AArch64][SVE] Add SVE2 intrinsics for bit permutation & table lookup
Summary:
Implements the following intrinsics:
 - @llvm.aarch64.sve.bdep.x
 - @llvm.aarch64.sve.bext.x
 - @llvm.aarch64.sve.bgrp.x
 - @llvm.aarch64.sve.tbl2
 - @llvm.aarch64.sve.tbx

The SelectTableSVE2 function in this patch is used to select the TBL2
intrinsic & ensures that the vector registers allocated are consecutive.

Reviewers: sdesmalen, andwar, dancgr, cameron.mcinally, efriedma, rengolin

Reviewed By: efriedma

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74912
2020-02-26 11:22:23 +00:00