Commit Graph

52281 Commits

Author SHA1 Message Date
Lang Hames 1997de0100 Fixed macro condition.
llvm-svn: 148408
2012-01-18 19:48:31 +00:00
Jim Grosbach e2d298168c Tidy up. 80 columns.
llvm-svn: 148401
2012-01-18 18:52:20 +00:00
Jim Grosbach aba3de99c0 Tidy up. MCAsmBackend naming conventions.
llvm-svn: 148400
2012-01-18 18:52:16 +00:00
Bill Wendling 75afc7afe8 Remove dead code.
llvm-svn: 148384
2012-01-18 10:10:28 +00:00
Nadav Rotem 3b8f0cc9fa Fix a bug in the type-legalization of vector integers. When we bitcast one vector type to another, we must not bitcast the result if one type is widened while the other is promoted.
llvm-svn: 148383
2012-01-18 08:33:18 +00:00
Pete Cooper c52eeed310 Fix ISD::REG_SEQUENCE to accept physical registers and change TwoAddressInstructionPass to insert copies for any physical reg operands of the REG_SEQUENCE
llvm-svn: 148377
2012-01-18 04:16:16 +00:00
Jim Grosbach adcc938c46 Thumb2 load/store fixups don't set the thumb bit.
Load/store instructions w/ a fixup to be relative a function marked as thumb
don't use the low bit to specify thumb vs. non-thumb like interworking
branches do, so don't set it when dealing with those fixups.

rdar://10348687.

llvm-svn: 148366
2012-01-18 00:40:25 +00:00
Jim Grosbach 3b50c9ec7f Move some ARM specific MCAssmebler bits into the ARMAsmBackend.
llvm-svn: 148364
2012-01-18 00:23:57 +00:00
Jakob Stoklund Olesen f43b599550 Add a CoveredBySubRegs property to Register descriptions.
When set, this bit indicates that a register is completely defined by
the value of its sub-registers.

Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers.  For example, the
ARM registers D8-D15 are callee-saved.  This now automatically implies
that Q4-Q7 are call-preserved.

Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.

llvm-svn: 148363
2012-01-18 00:16:39 +00:00
Jakob Stoklund Olesen fdbb12b235 Implement ARMBaseRegisterInfo::getCallPreservedMask().
Move ARM callee-saved lists into ARMCallingConv.td.

llvm-svn: 148357
2012-01-17 23:09:00 +00:00
Jim Grosbach 3fa6dcfebb Fix MCJIT memory leak of owned TargetMachine.
The JIT is expected to take ownership of the TM that's passed in. The MCJIT
wasn't freeing it, resulting in leaks.

llvm-svn: 148356
2012-01-17 23:08:46 +00:00
Jakob Stoklund Olesen d51a710bde Move X86 callee saved register lists to the X86CallConv .td file.
Add a trivial implementation of the getCallPreservedMask() hook.

llvm-svn: 148347
2012-01-17 22:47:01 +00:00
Jakub Staszak 173bce3d2b Move includes to the .cpp file.
llvm-svn: 148342
2012-01-17 22:16:31 +00:00
Jim Grosbach 4045507fea MC tweak symbol difference resolution for non-local symbols.
When the non-local symbol in the expression is in the same fragment
as the second symbol, the assembler can still evaluate the expression
without needing a relocation.

For example, on ARM:
_foo:
	ldr lr, (_foo - 4)

rdar://10348687

llvm-svn: 148341
2012-01-17 22:14:39 +00:00
Devang Patel c9ed518792 Intel syntax: Fix parser match class to check memory operand size.
llvm-svn: 148338
2012-01-17 21:48:03 +00:00
Nadav Rotem fb6ddee0e9 Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
llvm-svn: 148337
2012-01-17 21:44:01 +00:00
Devang Patel a7143b6a2b Intel syntax: Parse "BYTE PTR [RDX + RCX]"
llvm-svn: 148334
2012-01-17 21:25:10 +00:00
Dan Gohman e7a243fea5 Add a new ObjC ARC optimization pass to eliminate unneeded
autorelease push+pop pairs.

llvm-svn: 148330
2012-01-17 20:52:24 +00:00
Dan Gohman b9936296d3 Add a new PassManagerBuilder customization point,
EP_ModuleOptimizerEarly, to allow passes to be added before the
main ModulePass optimizers.

llvm-svn: 148329
2012-01-17 20:51:32 +00:00
Devang Patel 2ed6718616 Untabify.
llvm-svn: 148322
2012-01-17 19:09:22 +00:00
Devang Patel 8b39be79ad Intel syntax: Do not unncessarily create plus expression for memory operand displacement.
llvm-svn: 148321
2012-01-17 19:08:07 +00:00
Devang Patel 41b9ddeb7a Intel syntax: Robustify memory operand parsing.
llvm-svn: 148312
2012-01-17 18:00:18 +00:00
Manuel Klimek 85d26f9807 Removes template magic to build up containers.
Instead, we now put the attributes of the container into members.

llvm-svn: 148302
2012-01-17 09:34:07 +00:00
Nadav Rotem 86c3807b99 Fix warning.
llvm-svn: 148301
2012-01-17 09:31:09 +00:00
Nadav Rotem 86e5390dbf Fix 11769.
In CanXFormVExtractWithShuffleIntoLoad we assumed that EXTRACT_VECTOR_ELT can be later handled by the DAGCombiner.
However, in some cases on AVX, the EXTRACT_VECTOR_ELT is legalized to EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which
currently is not handled by the DAGCombiner. In this patch I added a check that we only extract from the XMM part.

llvm-svn: 148298
2012-01-17 09:13:19 +00:00
Craig Topper 02cb0fb136 Teach DAG combiner to turn a BUILD_VECTOR of UNDEFs into an UNDEF of vector type.
llvm-svn: 148297
2012-01-17 09:09:48 +00:00
Craig Topper 9cafcd8baa Remove unnecessary AVX check from an assert. hasSSE2 is enough.
llvm-svn: 148295
2012-01-17 08:23:44 +00:00
David Blaikie a5708dc3a3 Provide better messages in llvm_unreachable.
llvm-svn: 148293
2012-01-17 07:00:13 +00:00
Andrew Trick 7ccdc5c192 misched: Inital interface and implementation for ScheduleTopDownLive and ShuffleInstructions.
llvm-svn: 148291
2012-01-17 06:55:07 +00:00
Andrew Trick e1c034fefe Renamed MachineScheduler to ScheduleTopDownLive.
Responding to code review.

llvm-svn: 148290
2012-01-17 06:55:03 +00:00
Andrew Trick 8093eac51d Moving options declarations around.
More short term hackery until we have a way to configure passes that work on LiveIntervals.

llvm-svn: 148289
2012-01-17 06:54:59 +00:00
Andrew Trick 12728f04ca LSR fix: broaden the check for loop preheaders.
It's becoming clear that LoopSimplify needs to unconditionally create loop preheaders. But that is a bigger fix. For now, continuing to hack LSR.
Fixes rdar://10701050 "Cannot split an edge from an IndirectBrInst" assert.

llvm-svn: 148288
2012-01-17 06:45:52 +00:00
Craig Topper 37b10ef250 Fix a crasher when PerformShiftCombine receives a BUILD_VECTOR of all UNDEF. Probably could use better handling in DAG combine or getNode. Fixes PR11772.
llvm-svn: 148285
2012-01-17 04:44:50 +00:00
David Blaikie b48ed1a4cb Remove unreachable code. (replace with llvm_unreachable to help GCC where necessary)
llvm-svn: 148284
2012-01-17 04:43:56 +00:00
Rafael Espindola cbda0e255d Add 148175 back. I am unable to reproduce any non determinism in a dragonegg
or clang bootstrap.

I will keep an eye on the bots.

Original message:
Only emit the Leh_func_endN symbol when needed.

llvm-svn: 148283
2012-01-17 04:19:20 +00:00
Pete Cooper e3d305a206 Changed flag operand of ISD::FP_ROUND to TargetConstant as it should not get checked for legalisation
llvm-svn: 148275
2012-01-17 01:54:07 +00:00
Lang Hames 818e1ffd74 Fix typo in comment.
llvm-svn: 148268
2012-01-17 00:39:29 +00:00
Jim Grosbach 06594e1018 Tidy up.
llvm-svn: 148265
2012-01-16 23:50:58 +00:00
Jim Grosbach 0ddb3a4963 ExecutionEngine interface to re-map addresses for engines that support it.
llvm-svn: 148264
2012-01-16 23:50:55 +00:00
Jim Grosbach 9df6cc8f4f MCJIT handle a few more simple x86 relocations for MachO.
llvm-svn: 148263
2012-01-16 23:50:49 +00:00
David Blaikie 486df738c3 Removing unused default switch cases in switches over enums that already account for all enumeration values explicitly.
(This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them)

llvm-svn: 148262
2012-01-16 23:24:27 +00:00
Hal Finkel b1691ccaaa Cleanup PPC RLWINM8 vs RLWINM
No test case: output assembly will be identical.

llvm-svn: 148261
2012-01-16 23:22:50 +00:00
Hal Finkel 8606e3c7e3 AggressiveAntiDepBreaker needs to skip debug values because a debug value does not have a corresponding SUnit
llvm-svn: 148260
2012-01-16 22:53:41 +00:00
Jakob Stoklund Olesen 86ae07f049 Extract method for detecting constant unallocatable physregs.
It is safe to move uses of such registers.

llvm-svn: 148259
2012-01-16 22:34:08 +00:00
Jim Grosbach eff0a40d7e MCJIT support for non-function sections.
Move to a by-section allocation and relocation scheme. This allows
better support for sections which do not contain externally visible
symbols.

Flesh out the relocation address vs. local storage address separation a
bit more as well. Remote process JITs use this to tell the relocation
resolution code where the code will live when it executes.

The startFunctionBody/endFunctionBody interfaces to the JIT and the
memory manager are deprecated. They'll stick around for as long as the
old JIT does, but the MCJIT doesn't use them anymore.

llvm-svn: 148258
2012-01-16 22:26:39 +00:00
Stepan Dyatkovskiy 2931a59ec5 Fixed comment in loop-unswitch.
llvm-svn: 148252
2012-01-16 20:48:04 +00:00
Jakob Stoklund Olesen 6de6d3e4ec Give better scavenger errors by invoking the verifier.
llvm-svn: 148251
2012-01-16 20:38:31 +00:00
Jakob Stoklund Olesen 374ed322f2 Add a new kind of MachineOperand: MO_RegisterMask.
Register masks will be used as a compact representation of large clobber
lists.  Currently, an x86 call instruction has some 40 operands
representing call-clobbered registers.  That's more than 1kB of useless
operands per call site.

A register mask operand references a bit mask of call-preserved
registers, everything else is clobbered.  The bit mask will typically
come from TargetRegisterInfo::getCallPreservedMask().

By abandoning ImplicitDefs for call-clobbered registers, it also becomes
possible to share call instruction descriptions between calling
conventions, and we can get rid of the WINCALL* instructions.

This patch introduces the new operand kind.  Future patches will add
RegMask support to target-independent passes before finally the fixed
clobber lists can be removed from call instruction descriptions.

llvm-svn: 148250
2012-01-16 19:22:00 +00:00
Eli Friedman 206ca569aa Make sure the non-SSE lowering for fences correctly clobbers EFLAGS. PR11768.
llvm-svn: 148240
2012-01-16 16:42:21 +00:00
Eli Friedman 75e3db4c7a Get rid of unused codegen-only instruction.
llvm-svn: 148239
2012-01-16 16:29:35 +00:00