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9 Commits

Author SHA1 Message Date
Joerg Sonnenberger 22cd644e1b [SPARC] Both GNU and Solaris as support eq as condition code for integer ops. 
llvm-svn: 247804
 2015-09-16 14:41:36 +00:00
James Y Knight c09bdfa4cb Sparc: Prefer reg+reg address encoding when only one register used. 
Reg+%g0 is preferred to Reg+imm0 by the manual, and is what GCC produces.

Futhermore, reg+imm is invalid for the (not yet supported) "alternate
address space" instructions.

Differential Revision: http://reviews.llvm.org/D8753

llvm-svn: 236107
 2015-04-29 14:54:44 +00:00
James Y Knight e8da8096ec Sparc: Add alternate aliases for conditional branch instructions. 
llvm-svn: 236042
 2015-04-28 21:27:31 +00:00
Venkatraman Govindaraju 07d3af2821 [Sparc] Add return/rett instruction to Sparc backend. 
llvm-svn: 202666
 2014-03-02 22:55:53 +00:00
Venkatraman Govindaraju 2286874119 [Sparc] Add support for parsing annulled branch instructions. 
llvm-svn: 202599
 2014-03-01 20:08:48 +00:00
Venkatraman Govindaraju 0d288d3105 [Sparc] Add support for parsing jmpl instruction and make indirect call and jmp instructions as aliases to jmpl. 
llvm-svn: 198909
 2014-01-10 01:48:17 +00:00
Venkatraman Govindaraju b3b7c38983 [Sparc] Add support for parsing branch instructions and conditional moves. 
llvm-svn: 198738
 2014-01-08 06:14:52 +00:00
Venkatraman Govindaraju 559c4ac377 [Sparc] Add support for parsing sparc asm modifiers such as %hi, %lo etc., 
Also, correct the offsets for FixupsKindInfo.

llvm-svn: 198681
 2014-01-07 08:00:49 +00:00
Venkatraman Govindaraju 0458b599f8 [Sparc] Add support for parsing memory operands in sparc AsmParser. 
llvm-svn: 198658
 2014-01-07 01:49:11 +00:00