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Author SHA1 Message Date
Artem Belevich 236cfdc4be [CUDA] 32-bit NVPTX should have 32-bit long type. 
Currently it's 64-bit which will lead to mismatch between host and
device code if we compile for i386.

Differential Revision: http://reviews.llvm.org/D13181

llvm-svn: 248753
 2015-09-28 22:54:08 +00:00
Justin Holewinski bcb9055083 [NVPTX] Fix inline asm test case to use LLVM IR instead of PTX so it works even when the NVPTX target is not built 
llvm-svn: 184601
 2013-06-21 22:39:56 +00:00
Justin Holewinski 7ceab3a892 [NVPTX] Add NVPTX register constraints 
llvm-svn: 184578
 2013-06-21 18:51:24 +00:00