8740ee3637
Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.
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llvm-svn: 118160
2010-11-03 06:34:55 +00:00
dd6eb5b5a1
PR8359: The ARM backend may end up allocating registers D16 to D31 when
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"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers. Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!
llvm-svn: 116310
2010-10-12 16:22:47 +00:00
66e08d43d2
Jim Asked us to move DataLayout on ARM back to the most specialized classes. Do
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so and also change X86 for consistency.
Investigating if this can be improved a bit.
llvm-svn: 115469
2010-10-03 18:59:45 +00:00
97bf273870
Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits.
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LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned. Radar 8489376.
llvm-svn: 115047
2010-09-29 17:54:10 +00:00
a3181e2d79
Add a subtarget hook for reporting the misprediction penalty. Use this to provide more precise
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cost modeling for if-conversion. Now if only we had a way to estimate the misprediction probability.
Adjsut CodeGen/ARM/ifcvt10.ll. The pipeline on Cortex-A8 is long enough that it is still profitable
to predicate an ldm, but the shorter pipeline on Cortex-A9 makes it unprofitable.
llvm-svn: 114995
2010-09-28 21:57:50 +00:00
3dc97324c1
Add a command line option "-arm-strict-align" to disallow unaligned memory
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accesses for ARM targets that would otherwise allow it. Radar 8465431.
llvm-svn: 114941
2010-09-28 04:09:35 +00:00
6b2aaf1a36
Hard to imagine there are still people using inferior compilers.
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llvm-svn: 114862
2010-09-27 20:12:58 +00:00
69aa15155f
Odd additional stub framework for the ARM MC ELF emission.
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llc now recognizes the "intent" to support MC/obj emission for ARM, but
given that they are all stubs, it asserts on --filetype=obj --march=arm
Patch by Jason Kim.
llvm-svn: 114856
2010-09-27 18:31:37 +00:00
bf4070756f
Teach if-converter to be more careful with predicating instructions that would
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take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.
llvm-svn: 113570
2010-09-10 01:29:16 +00:00
4d5dc3e7e5
cortex m4 has floating point support, but only single precision.
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llvm-svn: 110810
2010-08-11 15:44:15 +00:00
5190f09291
Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors.
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llvm-svn: 110798
2010-08-11 07:17:46 +00:00
40921a4e62
Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.)
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llvm-svn: 110795
2010-08-11 06:51:54 +00:00
6e809de90c
- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the
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memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
instructions).
- Added tests for memory barrier codegen.
llvm-svn: 110785
2010-08-11 06:22:01 +00:00
ce8fb68078
Change -prefer-32bit-thumb to attribute -mattr=+32bit instead to disable more 32-bit to 16-bit optimizations.
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llvm-svn: 110584
2010-08-09 18:35:19 +00:00
58066e337d
Add an ARM "feature". Cortex-a8 fp comparison is very slow (> 20 cycles).
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llvm-svn: 108256
2010-07-13 19:21:50 +00:00
94231eec1f
Fix "warning: extra ';' inside a struct or union" when building llvm with clang
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llvm-svn: 103179
2010-05-06 14:57:47 +00:00
151cd8f159
Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack
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instructions to subtarget features and update tests to reflect.
PR5717.
llvm-svn: 103136
2010-05-05 23:44:43 +00:00
92d999001c
Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by
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Jordy <snhjordy@gmail.com>.
Followup patches will add some tests and adjust to use Subtarget features
for the instructions.
llvm-svn: 103119
2010-05-05 20:44:35 +00:00
bcaf681cde
Add const qualifiers to CodeGen's use of LLVM IR constructs.
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llvm-svn: 101334
2010-04-15 01:51:59 +00:00
a43386ba8f
switch the use-vml[as] instructions flag to a subtarget 'feature'
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llvm-svn: 99565
2010-03-25 23:11:16 +00:00
34de7768bf
Make the use of the vmla and vmls VFP instructions controllable via cmd line.
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Preliminary testing shows significant performance wins by not using these
instructions.
llvm-svn: 99436
2010-03-24 22:31:46 +00:00
0a65a37344
Add substarget feature for FP16
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llvm-svn: 98503
2010-03-14 18:42:38 +00:00
c499fae068
Lower small memcpys to load/stores on Thumb2.
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Radar 7686922.
llvm-svn: 98210
2010-03-11 00:20:49 +00:00
bf16a17fc1
Initial bits of ARMv4-only support.
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Patch by John Tytgat!
llvm-svn: 97886
2010-03-06 19:39:36 +00:00
505ddaa4dc
Remove isProfitableToDuplicateIndirectBranch target hook. It is profitable
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for all the processors where I have tried it, and even when it might not help
performance, the cost is quite low. The opportunities for duplicating
indirect branches are limited by other factors so code size does not change
much due to tail duplicating indirect branches aggressively.
llvm-svn: 90144
2009-11-30 18:35:03 +00:00
2522908653
Materialize global addresses via movt/movw pair, this is always better
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than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.
This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).
llvm-svn: 89720
2009-11-24 00:44:37 +00:00
290e9a47a9
Add a target hook to allow changing the tail duplication limit based on the
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contents of the block to be duplicated. Use this for ARM Cortex A8/9 to
be more aggressive tail duplicating indirect branches, since it makes it
much more likely that they will be predicted in the branch target buffer.
Testcase coming soon.
llvm-svn: 89187
2009-11-18 03:34:27 +00:00
b9fe5d5d02
Allow target to specify regclass for which antideps will only be broken along the critical path.
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llvm-svn: 88682
2009-11-13 19:52:48 +00:00
0d412c2528
Fixed to address code review. No functional changes.
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llvm-svn: 86634
2009-11-10 00:48:55 +00:00
cf89db135e
Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies.
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llvm-svn: 86628
2009-11-10 00:15:47 +00:00
8370485db9
Break anti-dependence breaking out into its own class.
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llvm-svn: 85127
2009-10-26 16:59:04 +00:00
02ad4cb32e
Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.
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llvm-svn: 84911
2009-10-22 23:19:17 +00:00
007ceb4603
Change createPostRAScheduler so it can be turned off at llc -O1.
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llvm-svn: 84273
2009-10-16 21:06:15 +00:00
17199b56b0
Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.
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llvm-svn: 83122
2009-09-30 00:10:16 +00:00
1b38952c99
Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172.
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llvm-svn: 80904
2009-09-03 07:04:02 +00:00
43b9ca6f42
Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer.
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llvm-svn: 80404
2009-08-28 23:18:09 +00:00
f24f9d9cb6
Whitespace cleanup. Remove trailing whitespace.
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llvm-svn: 78666
2009-08-11 15:33:49 +00:00
a307edbdd5
By default, for cortex-a8 use NEON for single-precision FP.
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llvm-svn: 78200
2009-08-05 16:01:19 +00:00
3b9c52c5c1
Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.
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llvm-svn: 78081
2009-08-04 17:53:06 +00:00
31b44e8f6c
Normalize Subtarget constructors to take a target triple string instead of
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Module*.
Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.
llvm-svn: 77918
2009-08-02 22:11:08 +00:00
3d8ccdb4be
isThumb2 really should mean thumb2 only, not thumb2+.
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llvm-svn: 74871
2009-07-06 22:29:14 +00:00
2c450d35ae
Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate.
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llvm-svn: 74692
2009-07-02 06:38:40 +00:00
8f74c88cb6
Revert 74164. We'll want to use this method later.
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llvm-svn: 74176
2009-06-25 16:03:07 +00:00
350abb9799
Remove unused hasV6T2Ops method. We already have a separate feature to
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identify Thumb2.
llvm-svn: 74164
2009-06-25 05:20:31 +00:00
4e712de541
Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits.
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llvm-svn: 73747
2009-06-19 01:51:50 +00:00
a0ca298f8a
Remove UseThumbBacktraces. Just check if subtarget is darwin.
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llvm-svn: 73734
2009-06-18 23:14:30 +00:00
409105fc95
Rename methods for the sake of consistency.
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llvm-svn: 73428
2009-06-15 21:46:20 +00:00
c82b282b34
Separate V6 from V6T2 since the latter has some extra nice instructions
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llvm-svn: 73085
2009-06-08 21:20:36 +00:00
cd41a9019e
Add helper for checking of Thumb1 mode
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llvm-svn: 73080
2009-06-08 20:31:02 +00:00
12694bd8ac
Implement review feedback. Make thumb2 'normal' subtarget feature
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llvm-svn: 72698
2009-06-01 20:00:48 +00:00
Evan Cheng