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276 Commits

Author SHA1 Message Date
Tom Stellard a99c6ae47a R600: Expand vselect for v4i32 and v2i32 
v2: Add vselect v4i32 test

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>

NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 181576
 2013-05-10 02:09:24 +00:00
Michel Danzer 7bbd7aa7fe R600/SI: Add lit tests for llvm.SI.imageload and llvm.SI.resinfo intrinsics 
Adapted from the llvm.SI.sample test.

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 181425
 2013-05-08 13:07:29 +00:00
Tom Stellard 043de4c5af R600: Emit config values in register / value pairs 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181228
 2013-05-06 17:50:51 +00:00
Tom Stellard cfe2ef8fea R600: Stop emitting the instruction type byte before each instruction 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181225
 2013-05-06 17:50:44 +00:00
Tom Stellard dbbcaf31b6 R600: Emit ISA for CALL_FS_* instructions 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181223
 2013-05-06 17:50:26 +00:00
Tom Stellard 4489b85f2b R600: Expand vector or, shl, srl, and xor nodes 
llvm-svn: 181035
 2013-05-03 17:21:31 +00:00
Tom Stellard eac65dde30 R600: Add pattern for SHA-256 Ma function 
This can be optimized using the BFI_INT instruction.

llvm-svn: 181033
 2013-05-03 17:21:20 +00:00
Vincent Lejeune ddd43383ef R600: Signed literals are 64bits wide 
llvm-svn: 180960
 2013-05-02 21:53:03 +00:00
Vincent Lejeune 2a44ae0053 R600: If previous bundle is dot4, PV valid chan is always X 
llvm-svn: 180959
 2013-05-02 21:52:55 +00:00
Vincent Lejeune 7cedb7161d R600: Add a test to check that use_kill is emitted 
llvm-svn: 180958
 2013-05-02 21:52:46 +00:00
Vincent Lejeune f97af796a9 R600: Prettier asmPrint of Alu 
llvm-svn: 180956
 2013-05-02 21:52:30 +00:00
Manman Ren 1a5ff287fd TBAA: remove !tbaa from testing cases if not used. 
This will make it easier to turn on struct-path aware TBAA since the metadata
format will change.

llvm-svn: 180796
 2013-04-30 17:52:57 +00:00
Vincent Lejeune e69e26025e R600: fix loop-address.ll test 
Texture cache is now used when shader type is not specified

llvm-svn: 180785
 2013-04-30 12:47:56 +00:00
Vincent Lejeune 3abdbf1cad R600: use native for alu 
llvm-svn: 180761
 2013-04-30 00:14:38 +00:00
Vincent Lejeune c299164284 R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions 
v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache

llvm-svn: 180755
 2013-04-30 00:13:39 +00:00
Tom Stellard 119ad03c67 R600: Use correct CF_END instruction on Northern Island GPUs 
llvm-svn: 180735
 2013-04-29 22:23:58 +00:00
Tom Stellard 8367067e02 R600: Fix encoding of CF_END_{EG, R600} instructions 
The EOP bit was not being encoded.

llvm-svn: 180734
 2013-04-29 22:23:54 +00:00
Tom Stellard 456adc6c4e R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTE 
We need to intialize this to something and since clang does not set
the shader type attribute and clang is used only for compute shaders,
initializing it to COMPUTE seems like the best choice.

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 180620
 2013-04-26 18:32:24 +00:00
Tom Stellard 34e4068d05 R600: Use SHT_PROGBITS for the .AMDGPU.config section 
The libelf implementation that is distributed here:
http://www.mr511.de/software/english.html
will not parse sections that are marked SHT_NULL.

llvm-svn: 180230
 2013-04-24 23:56:14 +00:00
Vincent Lejeune 117f075f6e R600: Use .AMDGPU.config section to emit stacksize 
llvm-svn: 180124
 2013-04-23 17:34:12 +00:00
Vincent Lejeune b6bfe85a07 R600: Add CF_END 
llvm-svn: 180123
 2013-04-23 17:34:00 +00:00
Tom Stellard 9d10c4ce86 R600: Add pattern for the BFI_INT instruction 
llvm-svn: 179830
 2013-04-19 02:11:06 +00:00
Tom Stellard 5a6b0d828b R600: Reorganize lit tests and document how they should be organized 
llvm-svn: 179828
 2013-04-19 02:10:53 +00:00
Vincent Lejeune 2d5c341cee R600: Make Export Instruction not duplicable 
llvm-svn: 179686
 2013-04-17 15:17:39 +00:00
Tom Stellard cb97e3acfa R600/SI: Emit config values in register value pairs. 
Instead of emitting config values in a predefined order, the code
emitter will now emit a 32-bit register index followed by the 32-bit
config value.

llvm-svn: 179546
 2013-04-15 17:51:35 +00:00
Tom Stellard 3a7beafb32 R600/SI: Emit configuration value in the .AMDGPU.config ELF section 
llvm-svn: 179545
 2013-04-15 17:51:30 +00:00
Tom Stellard 9991659fab R600: Emit ELF formatted code rather than raw ISA. 
llvm-svn: 179544
 2013-04-15 17:51:21 +00:00
Michel Danzer 8caa904bde R600/SI: Add pattern for AMDGPUurecip 
21 more little piglits with radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 179186
 2013-04-10 17:17:56 +00:00
Vincent Lejeune 04d9aa4822 R600: Add VTX_READ_* and RAT_WRITE_CACHELESS_* when computing cf addr 
llvm-svn: 179174
 2013-04-10 13:29:20 +00:00
Christian Konig 8b1ed28ef1 R600/SI: dynamical figure out the reg class of MIMG 
Depending on the number of bits set in the writemask.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 179166
 2013-04-10 08:39:16 +00:00
Christian Konig 8e06e2a8c4 R600/SI: adjust writemask to only the used components 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 179165
 2013-04-10 08:39:08 +00:00
Christian Konig 4ace663255 R600/SI: remove image sample writemask 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 179164
 2013-04-10 08:39:01 +00:00
Tom Stellard 754f80ff3a R600/SI: Add support for buffer stores v2 
v2:
  - Use the ADDR64 bit

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178931
 2013-04-05 23:31:51 +00:00
Tom Stellard 2f21c7e551 R600/SI: Add processor types for each SI variant 
Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178928
 2013-04-05 23:31:35 +00:00
Tom Stellard edbf1eb42b R600/SI: Avoid generating S_MOVs with 64-bit immediates v2 
SITargetLowering::analyzeImmediate() was converting the 64-bit values
to 32-bit and then checking if they were an inline immediate.  Some
of these conversions caused this check to succeed and produced
S_MOV instructions with 64-bit immediates, which are illegal.

v2:
  - Clean up logic

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178927
 2013-04-05 23:31:20 +00:00
Vincent Lejeune c44fa99719 R600: Take export into account when computing cf address 
llvm-svn: 178761
 2013-04-04 13:59:59 +00:00
Vincent Lejeune c3d3f9b66e R600: Fix last ALU of a clause being emitted in a separate clause 
llvm-svn: 178675
 2013-04-03 18:24:47 +00:00
Vincent Lejeune bfaa63a6db R600: Add support for native control flow 
llvm-svn: 178505
 2013-04-01 21:48:05 +00:00
Vincent Lejeune f43bc57b66 R600: Emit CF_ALU and use true kcache register. 
llvm-svn: 178503
 2013-04-01 21:47:42 +00:00
Christian Konig 08f5929942 R600/SI: add SETO/SETUO patterns 
6 more piglit tests.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 178145
 2013-03-27 15:27:31 +00:00
Christian Konig 3c14580acb R600/SI: add cummuting of rev instructions 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 178127
 2013-03-27 09:12:59 +00:00
Christian Konig 70a5032c1b R600/SI: add mulhu/mulhs patterns 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 178126
 2013-03-27 09:12:51 +00:00
Christian Konig 20a7e6b764 R600/SI: add srl/sha patterns for SI 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 178125
 2013-03-27 09:12:44 +00:00
Christian Konig 727d06de1d R600/SI: mark most intrinsics as readnone v2 
They read from constant register space anyway.

v2: fix lit tests

Signed-off-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178020
 2013-03-26 14:03:57 +00:00
Michel Danzer 3de8ae38e6 R600: Fix up test/CodeGen/R600/llvm.pow.ll for r177730 
llvm-svn: 177736
 2013-03-22 15:24:16 +00:00
Vincent Lejeune 0a22bc4156 R600: Factorize code handling Const Read Port limitation 
llvm-svn: 177078
 2013-03-14 15:50:45 +00:00
NAKAMURA Takumi e781913ac4 llvm/test/CodeGen/R600/schedule-*.ll: Let them require +Asserts. 
llvm-svn: 176835
 2013-03-11 23:16:30 +00:00
Vincent Lejeune e5ecf10a02 R600: Fix JUMP handling so that MachineInstr verification can occur 
This allows R600 Target to use the newly created -verify-misched llc flag

llvm-svn: 176819
 2013-03-11 18:15:06 +00:00
Benjamin Kramer 01b75cc0f2 Test case hygiene. 
llvm-svn: 176772
 2013-03-09 18:25:40 +00:00
Tom Stellard 5e524897ed R600: Optimize another selectcc case 
fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
     selectcc x, y, a, b, cc

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 176700
 2013-03-08 15:37:11 +00:00
Tom Stellard 2add82de09 R600: Improve custom lowering of select_cc 
Two changes:
1. Prefer SET* instructions when possible
2. Handle the CND*_INT case with floating-point args

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 176699
 2013-03-08 15:37:09 +00:00
Tom Stellard 492ebeabe9 R600: Change operation action from Custom to Expand for BR_CC 
Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 176698
 2013-03-08 15:37:07 +00:00
Tom Stellard e8f9f2877b R600: Change operation action from Custom to Expand for SETCC 
Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 176697
 2013-03-08 15:37:05 +00:00
Tom Stellard d93ef7afaa LegalizeDAG: Respect the result of TLI.getBooleanContents() when expanding SETCC 
llvm-svn: 176695
 2013-03-08 15:37:02 +00:00
Vincent Lejeune 2bc2730765 R600: Change addresspace in fold-kcache.ll 
AddressSpace definition has changed in a previous commit, reflect it
to avoid false failure.

llvm-svn: 176693
 2013-03-08 15:34:07 +00:00
Christian Konig 21442994a7 R600/SI: adjust test to recent changes 
Signed-off-by: Christian König <christian.koenig@amd.com>
llvm-svn: 176691
 2013-03-08 14:44:00 +00:00
Vincent Lejeune 3b6f20e944 R600: Turn BUILD_VECTOR into Reg_Sequence 
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 176487
 2013-03-05 15:04:49 +00:00
Vincent Lejeune a199d01e4d R600: Use MUL_IEEE for trig/fdiv intrinsic 
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 176485
 2013-03-05 15:04:37 +00:00
Christian Konig 3c54770365 R600/SI: fix sampler tests after fixing wait insertions 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 176359
 2013-03-01 17:39:05 +00:00
Tom Stellard 0d171c8877 R600: Fix for Unigine when MachineSched is enabled 
Fixes for-loop.cl piglit test

Patch By: Vincent Lejeune

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

NOTE: This is a candidate for the Mesa stable branch.
llvm-svn: 175742
 2013-02-21 15:06:59 +00:00
Michel Danzer 7f02a8c7a7 R600/SI: Make sure M0 is loaded for V_INTERP_MOV_F32 
NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 175733
 2013-02-21 08:57:10 +00:00
Vincent Lejeune 1ce13f553e R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad pattern 
llvm-svn: 175446
 2013-02-18 14:11:28 +00:00
Vincent Lejeune f940fd05bd R600: Do not fold single instruction with more that 3 kcache read 
It fixes around 100 tfb piglit tests and 16 glean tests.

NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 175183
 2013-02-14 16:57:19 +00:00
Michel Danzer 51d5eb2f63 R600: Add lit tests for texture sampling instruction selection. 
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 175138
 2013-02-14 07:43:51 +00:00
Tom Stellard 91da4e9199 R600: Add support for 128-bit parameters 
NOTE: This is a candidate for the Mesa stable branch.
llvm-svn: 175096
 2013-02-13 22:05:20 +00:00
Tom Stellard e06163a9a6 R600: Add support for SET*_DX10 instructions 
These instructions compare two floating point values and return an
integer true (-1) or false (0) value.

When compiling code generated by the Mesa GLSL frontend, the SET*_DX10
instructions save us four instructions for most branch decisions that
use floating-point comparisons.

llvm-svn: 174609
 2013-02-07 14:02:35 +00:00
Tom Stellard 6d867e8d4d R600: Add tests for unsupported condition codes. 
All of the le and lt variants are unsupported.

llvm-svn: 174608
 2013-02-07 14:02:33 +00:00
Tom Stellard b40ada9b85 R600: Fix assembly name for SETGT_INT 
llvm-svn: 174607
 2013-02-07 14:02:27 +00:00
Tom Stellard 7d41161a2d R600: Add tests for instruction predicates 
llvm-svn: 174393
 2013-02-05 17:09:13 +00:00
Tom Stellard 2e5e7a5bef R600: Emit function name in the AsmPrinter 
Emitting the function name allows us to check for it in the FileCheck
tests so we can make sure FileCheck is checking the output of the
correct function.

llvm-svn: 174392
 2013-02-05 17:09:11 +00:00
Tom Stellard 4926921bd4 R600: Fold clamp, neg, abs 
Patch by: Vincent Lejeune

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174099
 2013-01-31 22:11:54 +00:00
Tom Stellard 567f886eb0 DAGCombiner: Avoid generating illegal vector INT_TO_FP nodes 
DAGCombiner::reduceBuildVecConvertToConvertBuildVec() was making two
mistakes:

1. It was checking the legality of scalar INT_TO_FP nodes and then generating
vector nodes.

2. It was passing the result value type to
TargetLoweringInfo::getOperationAction() when it should have been
passing the value type of the first operand.

llvm-svn: 171420
 2013-01-02 22:13:01 +00:00
Tom Stellard a8b0351720 R600: Expand vec4 INT <-> FP conversions 
llvm-svn: 170901
 2012-12-21 16:33:24 +00:00
Tom Stellard 75aadc2813 Add R600 backend 
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX

llvm-svn: 169915
 2012-12-11 21:25:42 +00:00
Tom Stellard fc3db614c0 Revert "test/CodeGen/R600: Add some basic tests v6" 
This reverts commit 11d3457afcda7848448dd7f11b2ede6552ffb9ea.

llvm-svn: 160300
 2012-07-16 18:19:43 +00:00
Tom Stellard 6693fbe3eb test/CodeGen/R600: Add some basic tests v6 
llvm-svn: 160273
 2012-07-16 14:17:19 +00:00