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8 Commits

Author SHA1 Message Date
Vincent Lejeune 7e2c83256b R600: Non vector only instruction can be scheduled on trans unit 
llvm-svn: 189980
 2013-09-04 19:53:46 +00:00
Tom Stellard ca69a53bae Revert "R600: Non vector only instruction can be scheduled on trans unit" 
This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6.

llvm-svn: 187526
 2013-07-31 20:43:27 +00:00
Vincent Lejeune df18804e26 R600: Non vector only instruction can be scheduled on trans unit 
llvm-svn: 187514
 2013-07-31 19:31:56 +00:00
Vincent Lejeune f97af796a9 R600: Prettier asmPrint of Alu 
llvm-svn: 180956
 2013-05-02 21:52:30 +00:00
Tom Stellard 492ebeabe9 R600: Change operation action from Custom to Expand for BR_CC 
Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 176698
 2013-03-08 15:37:07 +00:00
Tom Stellard e8f9f2877b R600: Change operation action from Custom to Expand for SETCC 
Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 176697
 2013-03-08 15:37:05 +00:00
Tom Stellard e06163a9a6 R600: Add support for SET*_DX10 instructions 
These instructions compare two floating point values and return an
integer true (-1) or false (0) value.

When compiling code generated by the Mesa GLSL frontend, the SET*_DX10
instructions save us four instructions for most branch decisions that
use floating-point comparisons.

llvm-svn: 174609
 2013-02-07 14:02:35 +00:00
Tom Stellard 75aadc2813 Add R600 backend 
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX

llvm-svn: 169915
 2012-12-11 21:25:42 +00:00