e4ce92cabf
[Hexagon] Allow construction of HVX vector predicates
...
Handle BUILD_VECTOR of boolean values.
llvm-svn: 321220
2017-12-20 20:49:43 +00:00
6b589e593d
[Hexagon] Generate HVX code for vector sign-, zero- and any-extends
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Implement any-extend as zero-extend.
llvm-svn: 321004
2017-12-18 18:32:27 +00:00
470760533a
[Hexagon] Generate HVX code for comparisons and selects
...
llvm-svn: 320744
2017-12-14 21:28:48 +00:00
708c9f5947
[Hexagon] Remove vectors of i64 from valid HVX types
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HVX does not support operations on 64-bit integers.
llvm-svn: 320722
2017-12-14 18:35:24 +00:00
152414595b
[Hexagon] Crash in instruction selection for insert_vector_elt for HVX
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A wrong type was passed to insertVector, causing an out-of-bounds value
to be added an an operand to HexagonISD::INSERT. This later failed in
instruction selection.
llvm-svn: 320369
2017-12-11 14:46:06 +00:00
039d4d9286
[Hexagon] Generate HVX code for basic arithmetic operations
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Handle and, or, xor, add, sub, mul for vectors of i8, i16, and i32.
llvm-svn: 320063
2017-12-07 17:37:28 +00:00
7654ed03e3
[Hexagon] Suppress warnings on unused variables defind for asserts.
...
llvm-svn: 319940
2017-12-06 19:22:19 +00:00
7d37dd8902
[Hexagon] Generate HVX code for vector construction and access
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Support for:
- build vector,
- extract vector element, subvector,
- insert vector element, subvector,
- shuffle.
llvm-svn: 319901
2017-12-06 16:40:37 +00:00
Krzysztof Parzyszek