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6 Commits

Author SHA1 Message Date
Eric Christopher c206d46709 Make the 'x' constraint work for AVX registers as well. 
Fixes rdar://10614894

llvm-svn: 147704
 2012-01-07 01:02:09 +00:00
Eric Christopher 9da7f305a4 For 64-bit the rest of the general regs are ok for the q constraint. Make 
sure we can emit both the high and low versions of those registers.

Fixes rdar://10392864

llvm-svn: 145579
 2011-12-01 08:12:41 +00:00
Nick Lewycky 9badf60203 Let the inline asm 'q' constraint match float, and on 64-bit double too. 
Fixes PR9602!

llvm-svn: 134665
 2011-07-08 00:19:27 +00:00
Chris Lattner 8936d2bfbc Remove support for parsing the "type i32" syntax for defining a numbered 
top level type without a specified number.  This syntax isn't documented
and blocks forward progress.

llvm-svn: 133371
 2011-06-19 00:03:46 +00:00
Dan Gohman 40503396da Eliminate more uses of llvm-as and llvm-dis. 
llvm-svn: 81290
 2009-09-08 23:54:48 +00:00
Evan Cheng 18fe458103 Fix x86 inline ams 'q' constraint support. In 32-bit mode, it's just like 'Q', i.e. EAX, EDX, ECX, EBX. In 64-bit mode, it just means all the i64r registers. Yeah, that makes sense. 
llvm-svn: 76248
 2009-07-17 22:13:25 +00:00