Commit Graph

120 Commits

Author SHA1 Message Date
Chris Lattner e99faac423 don't do ReplaceUses on a result that doesn't exist.
llvm-svn: 46673
2008-02-03 03:20:59 +00:00
Evan Cheng efd142a920 SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.

llvm-svn: 46659
2008-02-02 04:07:54 +00:00
Dan Gohman 47a7d6fafe Factor the addressing mode and the load/store VT out of LoadSDNode
and StoreSDNode into their common base class LSBaseSDNode. Member
functions getLoadedVT and getStoredVT are replaced with the common
getMemoryVT to simplify code that will handle both loads and stores.

llvm-svn: 46538
2008-01-30 00:15:11 +00:00
Chris Lattner a10fff51d9 Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled.  Given this expanded name, we can start 
moving other stuff into it.  For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.

Update all the clients to match.

This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.

llvm-svn: 45467
2007-12-31 04:13:23 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev.
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Dan Gohman a160361c85 Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.

llvm-svn: 42762
2007-10-08 18:33:35 +00:00
Evan Cheng 9d41b311fb Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
llvm-svn: 38501
2007-07-10 18:08:01 +00:00
Evan Cheng 7e90b11550 Unfortunately we now require C++ code to isel Bcc, conditional moves, etc.
llvm-svn: 37896
2007-07-05 07:15:27 +00:00
Evan Cheng 0f7cbe8370 Add PredicateOperand to all ARM instructions that have the condition field.
llvm-svn: 37066
2007-05-15 01:29:07 +00:00
Chris Lattner 1c1082133c match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.ll
llvm-svn: 36660
2007-05-03 00:32:00 +00:00
Evan Cheng 9bb01c9f4f Fix naming inconsistencies.
llvm-svn: 35163
2007-03-19 07:48:02 +00:00
Evan Cheng ee2763f76f Special LDR instructions to load from non-pc-relative constantpools. These are
rematerializable. Only used for constant generation for now.

llvm-svn: 35162
2007-03-19 07:20:03 +00:00
Evan Cheng 72a8bcf238 AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2]
llvm-svn: 35088
2007-03-13 21:05:54 +00:00
Evan Cheng 62aef236de Get rid of references to iostream.
llvm-svn: 34009
2007-02-07 21:18:32 +00:00
Evan Cheng a974031ebd Select add FI, c correctly.
llvm-svn: 33960
2007-02-06 09:11:20 +00:00
Evan Cheng 650d0672f7 - Store val, [sp, c] must be selected to tSTRsp.
- If c does not fit in the offset field, materialize sp + c into a register
  using tADDhirr.

llvm-svn: 33944
2007-02-06 00:22:06 +00:00
Evan Cheng 1cd3c0efb8 Change the operand orders to t_addrmode_s* to make it easier to morph
instructions that use these address modes to instructions that use
t_addrmode_sp.

llvm-svn: 33651
2007-01-30 02:35:32 +00:00
Evan Cheng 1526ba50d9 Use PC relative ldr to load from a constantpool in Thumb mode.
llvm-svn: 33484
2007-01-24 08:53:17 +00:00
Evan Cheng 8942551dee Allow [ fi#c, imm ] as ARM load / store addresses.
llvm-svn: 33474
2007-01-24 02:45:25 +00:00
Evan Cheng 139edae4a2 Various Thumb mode load / store isel bug fixes.
llvm-svn: 33472
2007-01-24 02:21:22 +00:00
Evan Cheng c0b7366cf9 - Reorg Thumb load / store instructions. Combine each rr and ri pair of
instructions into one (e.g. tLDRrr, tLDRri -> tLDR).
- Thumb ldrsb and ldrsh only have the [reg, reg] address format. If the
  address is not an add, materialize a 0 immediate into a register and use
  it as the offset field.

llvm-svn: 33470
2007-01-23 22:59:13 +00:00
Evan Cheng 10043e215b ARM backend contribution from Apple.
llvm-svn: 33353
2007-01-19 07:51:42 +00:00
Lauro Ramos Venancio c4235e5521 Build constants using instructions mov/orr or mvn/eor.
llvm-svn: 33141
2007-01-12 20:35:49 +00:00
Lauro Ramos Venancio 7284073ec2 Expand SELECT (f32/f64) and FCOPYSIGN (f32/f64).
llvm-svn: 32870
2007-01-04 14:01:38 +00:00
Rafael Espindola fd68718467 implement missing compares
patch by Lauro
bug fixed by me

llvm-svn: 32795
2006-12-31 18:52:39 +00:00
Reid Spencer e63b6518fa For PR950:
Three changes:
1. Convert signed integer types to signless versions.
2. Implement the @sext and @zext parameter attributes. Previously the
   type of an function parameter was used to determine whether it should
   be sign extended or zero extended before the call. This information is
   now communicated via the function type's parameter attributes.
3. The interface to LowerCallTo had to be changed in order to accommodate
   the parameter attribute information. Although it would have been
   convenient to pass in the FunctionType itself, there isn't always one
   present in the caller. Consequently, a signedness indication for the
   result type and for each parameter was provided for in the interface
   to this method. All implementations were changed to make the adjustment
   necessary.

llvm-svn: 32788
2006-12-31 05:55:36 +00:00
Rafael Espindola 64493fb30d fix comment
llvm-svn: 32767
2006-12-29 14:28:12 +00:00
Lauro Ramos Venancio 7251e57ff8 Implement SELECT_CC (f32/f64) for ARM.
llvm-svn: 32762
2006-12-28 13:11:14 +00:00
Rafael Espindola 3b7544e24c avoid using a constant table when a constant can be used inline
llvm-svn: 32580
2006-12-14 18:58:37 +00:00
Rafael Espindola 67d1c8ae0e more general matching of the MVN instruction
llvm-svn: 32484
2006-12-12 17:10:13 +00:00
Rafael Espindola 470d61d82c don't use "ordinary" addressing mode 1 when mvn is appropriate
llvm-svn: 32482
2006-12-12 14:03:29 +00:00
Rafael Espindola 9fa0a26808 use MVN to handle small negative constants
llvm-svn: 32459
2006-12-12 01:03:11 +00:00
Bill Wendling 9bfb1e1f29 What should be the last unnecessary <iostream>s in the library.
llvm-svn: 32333
2006-12-07 22:21:48 +00:00
Rafael Espindola b5dee63958 expand memmove and memcpy
llvm-svn: 32226
2006-12-05 17:57:23 +00:00
Rafael Espindola 96fd6447c7 add support for the "r" asm constraint
patch by Lauro Ramos Venancio

llvm-svn: 32224
2006-12-05 17:37:31 +00:00
Rafael Espindola 5f7ab1b964 implement load effective address similar to the alpha backend
remove lea_addri and the now unused memri addressing mode

llvm-svn: 31592
2006-11-09 13:58:55 +00:00
Evan Cheng 6cd0909da7 Match tblegen changes.
llvm-svn: 31571
2006-11-08 20:34:28 +00:00
Rafael Espindola 708cb60588 initial implementation of addressing mode 2
TODO: fix lea_addri

llvm-svn: 31552
2006-11-08 17:07:32 +00:00
Rafael Espindola ac8668d62f move ARMCondCodeToString to ARMAsmPrinter.cpp
remove unused variables from lowerCall

llvm-svn: 31378
2006-11-02 15:00:02 +00:00
Evan Cheng 0d41d19427 All targets expand BR_JT for now.
llvm-svn: 31294
2006-10-30 08:02:39 +00:00
Rafael Espindola a23166d6a4 initial support for frame pointers
llvm-svn: 31197
2006-10-26 13:31:26 +00:00
Rafael Espindola bd29281e97 expand ISD::VACOPY
llvm-svn: 31170
2006-10-24 20:15:21 +00:00
Rafael Espindola cd5f662c7b expand ISD::MEMSET
llvm-svn: 31137
2006-10-23 20:08:22 +00:00
Reid Spencer e0fc4dfc22 For PR950:
This patch implements the first increment for the Signless Types feature.
All changes pertain to removing the ConstantSInt and ConstantUInt classes
in favor of just using ConstantInt.

llvm-svn: 31063
2006-10-20 07:07:24 +00:00
Rafael Espindola 3c563c5072 expand SIGN_EXTEND_INREG
llvm-svn: 31046
2006-10-19 12:06:50 +00:00
Rafael Espindola b260306625 expand brind so that we don't have to implement jump tables right now
llvm-svn: 31045
2006-10-19 10:56:43 +00:00
Rafael Espindola b21e8d2e12 implement CallingConv::Fast as CallingConv::C
llvm-svn: 31034
2006-10-18 12:03:07 +00:00
Rafael Espindola ba8f296167 expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM
llvm-svn: 31014
2006-10-17 21:05:33 +00:00
Rafael Espindola 19398ec86e initial implementation of addressing mode 5
llvm-svn: 31002
2006-10-17 18:04:53 +00:00
Rafael Espindola f719c5f43d expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS
llvm-svn: 30987
2006-10-16 21:10:32 +00:00