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Author SHA1 Message Date
Matt Arsenault 14fe4607f1 AMDGPU: Support commuting register and global operand 2020-07-01 13:59:13 -04:00
Matt Arsenault a21544ad11 AMDGPU: Fix handling of target flags when commuting instruction 
If the original register operand had a subregister, it wasn't getting
cleared. This resulted in reinterpreted the subreg index as
unrecognized target flags, which produced unparseable MIR.
 2020-07-01 13:59:13 -04:00