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6 Commits

Author SHA1 Message Date
Andrew Trick e97d8d6dde Enable MI Sched for x86. 
This changes the SelectionDAG scheduling preference to source
order. Soon, the SelectionDAG scheduler can be bypassed saving
a nice chunk of compile time.

Performance differences that result from this change are often a
consequence of register coalescing. The register coalescer is far from
perfect. Bugs can be filed for deficiencies.

On x86 SandyBridge/Haswell, the source order schedule is often
preserved, particularly for small blocks.

Register pressure is generally improved over the SD scheduler's ILP
mode. However, we are still able to handle large blocks that require
latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also
attempts to discover the critical path in single-block loops and
adjust heuristics accordingly.

The MI scheduler relies on the new machine model. This is currently
unimplemented for AVX, so we may not be generating the best code yet.

Unit tests are updated so they don't depend on SD scheduling heuristics.

llvm-svn: 192750
 2013-10-15 23:33:07 +00:00
Andrew Trick 121124acf8 Revert "Temporarily enable MI-Sched on X86." 
This reverts commit 98a9b72e8c56dc13a2617de84503a3d78352789c.

llvm-svn: 184823
 2013-06-25 02:48:58 +00:00
Andrew Trick 5a1e0af838 Temporarily enable MI-Sched on X86. 
Sorry for the unit test churn. I'll try to make the change permanently
next time.

llvm-svn: 184705
 2013-06-24 09:13:20 +00:00
Rafael Espindola 7f4f79a5bc Fix the cpu name and add -verify-machineinstrs. 
llvm-svn: 166003
 2012-10-16 01:13:06 +00:00
Rafael Espindola aee00b5e72 Add a cpu to try to fix the atom builder. 
llvm-svn: 165956
 2012-10-15 19:25:43 +00:00
Rafael Espindola b41459a3c0 Add testcase for pr14088. 
llvm-svn: 165954
 2012-10-15 19:00:10 +00:00